| Module 1 |
| L1 |
History of Calculation and Computer
Architecture (A) (PDF) |
| L2 |
Influence of Technology and Software on
Instruction Sets: Up to the dawn of IBM 360 (A) (PDF) |
| L3 |
Complex Instruction Set Evolution in
the Sixties: Stack and GPR Architectures (A) (PDF) |
| L4 |
Microprogramming (A) (PDF) |
| L5 |
Simple Instruction Pipelining (A) (PDF) |
| L6 |
Pipeline Hazards (A) (PDF)# |
| Module 2 |
| L7 |
Multilevel Memories - Technology (J) (PDF) |
| L8 |
Cache (Memory) Performance Optimization
(J) (PDF) |
| L9 |
Virtual Memory Basics (J) (PDF) |
| L10 |
Virtual Memory: Part Deux (A) (PDF) |
| Module 3 |
| L11 |
Complex Pipelining (A) (PDF) |
| L12 |
Out of Order Execution and Register
Renaming (A) (PDF) |
| L13 |
Branch Prediction and Speculative
Execution (A) (PDF) |
| L14 |
Advanced Superscalar Architectures (J) (PDF) |
| L15 |
Microprocessor Evolution: 4004 to
Pentium 4 (J) (PDF) |
| Module 4 |
| L16 |
Synchronization and Sequential
Consistency (A) (PDF) |
| L17 |
Cache Coherence (A) (PDF) |
| L18 |
Cache Coherence (Implementation) (A) (PDF) |
| L19 |
Snoopy Protocols (A) (PDF) |
| L20 |
Relaxed Memory Models (A) (PDF) |
| Module 5 |
| L21 |
VLIW/EPIC: Statically Scheduled ILP (J)
(PDF) |
| L22 |
Vector Computers (J) (PDF) |
| L23 |
Multithreaded Processors (J) (PDF) |
| L24 |
Reliable Architectures (J) (PDF) |
| L25 |
Virtual Machines (J) (PDF) |
