--- incoherent_ht.c.x	2004-03-25 14:03:49.000000000 -0800
+++ incoherent_ht.c	2004-03-25 13:31:24.000000000 -0800
@@ -182,7 +182,6 @@
 
 	return needs_reset;
 }
-
 static int ht_setup_chain(device_t udev, unsigned upos)
 {
 	/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
@@ -242,3 +241,126 @@
 	} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
 	return reset_needed;
 }
+struct ht_chain {
+        device_t udev;
+        unsigned upos;
+        unsigned devreg; 
+};             
+static int ht_setup_chainx(device_t udev, unsigned upos, unsigned next_unitid)
+{               
+        unsigned last_unitid;
+        unsigned uoffs;
+	int reset_needed=0;
+        
+
+        uoffs = PCI_HT_HOST_OFFS;
+        do {
+                uint32_t id;
+                uint8_t pos;
+                unsigned flags, count;
+                device_t dev = PCI_DEV(0, 0, 0);
+                last_unitid = next_unitid;
+
+                id = pci_read_config32(dev, PCI_VENDOR_ID);
+                /* If the chain is enumerated quit */
+                if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+                        (((id >> 16) & 0xffff) == 0xffff) ||
+                        (((id >> 16) & 0xffff) == 0x0000)) {
+                        break;
+                }
+                pos = ht_lookup_slave_capability(dev);
+                if (!pos) {
+                        print_err("HT link capability not found\r\n");
+                        break;
+                }
+                /* Setup the Hypertransport link */
+                reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, PCI_HT_SLAVE0_OFFS);
+
+                /* Update the Unitid of the current device */
+                flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
+                flags &= ~0x1f; /* mask out the bse Unit ID */
+                flags |= next_unitid & 0x1f;
+                pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
+
+                /* Remeber the location of the last device */
+                udev = PCI_DEV(0, next_unitid, 0);
+                upos = pos;
+                uoffs = PCI_HT_SLAVE1_OFFS;
+
+                /* Compute the number of unitids consumed */
+                count = (flags >> 5) & 0x1f;
+                next_unitid += count;
+
+        } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
+	if(reset_needed!=0) next_unitid |= 0xffff0000;
+        return next_unitid;
+} 
+static int ht_setup_chains(const struct ht_chain *ht_c, int ht_c_num)
+{               
+        /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. 
+         * On most boards this just happens.  If a cpu has multiple
+         * non Coherent links the appropriate bus registers for the
+         * links needs to be programed to point at bus 0.
+         */     
+        unsigned next_unitid;
+        int reset_needed; 
+        unsigned upos;
+        device_t udev;
+        int i;
+
+        /* Make certain the HT bus is not enumerated */
+        ht_collapse_previous_enumeration(0);
+
+        reset_needed = 0;
+        next_unitid = 1;
+
+
+        for(i=0;i<ht_c_num;i++) {
+		uint32_t reg;
+		uint8_t reg8;
+		reg = pci_read_config32(PCI_DEV(0,0x18,1), ht_c[i].devreg);
+		reg |= (0xff<<24) | 7;
+		reg &= ~(0xff<<16);
+        	pci_write_config32(PCI_DEV(0,0x18,1), ht_c[i].devreg, reg);
+#if CONFIG_MAX_CPUS > 1 
+		pci_write_config32(PCI_DEV(0,0x19,1), ht_c[i].devreg, reg);
+#endif
+#if CONFIG_MAX_CPUS > 2
+		pci_write_config32(PCI_DEV(0,0x1a,1), ht_c[i].devreg, reg);
+		pci_write_config32(PCI_DEV(0,0x1b,1), ht_c[i].devreg, reg);
+#endif
+		//Store dev min
+		reg8 = next_unitid & 0xff ;
+        	upos = ht_c[i].upos;
+        	udev = ht_c[i].udev;
+
+		next_unitid = ht_setup_chainx(udev,upos,next_unitid);
+	
+		if((next_unitid & 0xffff0000) == 0xffff0000) {
+			reset_needed |= 1;
+			next_unitid &=0x0000ffff;
+		}
+
+		//set dev min
+                pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg+2, reg8);
+#if CONFIG_MAX_CPUS > 1 
+                pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg+2, reg8);
+#endif
+#if CONFIG_MAX_CPUS > 2
+                pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg+2, reg8);
+                pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg+2, reg8);
+#endif	
+		//Set dev max
+		reg8 = (next_unitid-1) & 0xff ;
+        	pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg+3, reg8);
+#if CONFIG_MAX_CPUS > 1 
+        	pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg+3, reg8);
+#endif
+#if CONFIG_MAX_CPUS > 2
+        	pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg+3, reg8);
+        	pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg+3, reg8);
+#endif
+        }
+
+        return reset_needed;
+}