Hi Andre,
Thank you for the response. I actually just resolved this issue a few
days ago. The issue was just that the memory allocation for the DMA was
not done correctly, and thus the device was attempting to write to
unallocated space in some cases, causing undefined results.
The only reason I didn't realize it at the time was because the actual
allocation that was happening was obscured because of the way my
codebase had some preprocessor macros configured. After identifying that
issue, everything works as expected.
Thank you and have a great day,
Mitchell Augustin
On 10/26/23 18:29, Andre Przywara wrote:
On Wed, 18 Oct 2023 17:22:30 -0700 (PDT)
Mitchell Augustin <[email protected]> wrote:
Hi,
Hello, I'm writing an ethernet driver for a small embedded os called Xinu
on the Orange Pi (allwinner H3) and am running into an issue. I have set up
my RX ring and enabled the interrupts, and sometimes a few packets will get
received correctly, but after at most a few correct packets, I will start
receiving an RX_BUF_UA_INT interrupt. The hardware documentation says this
means "the RX DMA can't acquire the next RX descriptor".
*Question: What would cause the DMA to be unable to acquire an RX
descriptor?*
For context, my OS does not use any sort of virtual memory, so addresses
But are you running with the MMU and caches enabled? Do you do the
proper cache maintenance for the buffers? The platform peripherals in
the H3 (as in most ARM based devices) are not cache coherent, so you
(the CPU) or the device might read stale data.
This applies both to the DMA descriptors and the actual packets, because
they both live in normal memory.
Happy to explain in more detail if that might be your issue, just let me
know.
Cheers,
Andre
are directly mapped. My RX ring is a DMA-aligned, circular array of
descriptors in the descriptor format specified by the datasheet, and I have
set rx_dma_desc_list (address 0x34 in the EMAC CSR) to that descriptor list.
Any insight would be greatly appreciated. Thanks!
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