With the next commit another clock and reset driver will be implemented
which requires DE2 related clocks and resets. Add them.

Cc: Lukasz Majewski <[email protected]>
Signed-off-by: Jernej Skrabec <[email protected]>
---
 drivers/clk/sunxi/clk_a64.c | 6 ++++++
 drivers/clk/sunxi/clk_h3.c  | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 0553ffa4399a..c7cf88ce3436 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -26,6 +26,8 @@ static const struct ccu_clk_gate a64_gates[] = {
        [CLK_BUS_OHCI0]         = GATE(0x060, BIT(28)),
        [CLK_BUS_OHCI1]         = GATE(0x060, BIT(29)),
 
+       [CLK_BUS_DE]            = GATE(0x064, BIT(12)),
+
        [CLK_BUS_UART0]         = GATE(0x06c, BIT(16)),
        [CLK_BUS_UART1]         = GATE(0x06c, BIT(17)),
        [CLK_BUS_UART2]         = GATE(0x06c, BIT(18)),
@@ -41,6 +43,8 @@ static const struct ccu_clk_gate a64_gates[] = {
        [CLK_USB_HSIC_12M]      = GATE(0x0cc, BIT(11)),
        [CLK_USB_OHCI0]         = GATE(0x0cc, BIT(16)),
        [CLK_USB_OHCI1]         = GATE(0x0cc, BIT(17)),
+
+       [CLK_DE]                = GATE(0x104, BIT(31)),
 };
 
 static const struct ccu_reset a64_resets[] = {
@@ -60,6 +64,8 @@ static const struct ccu_reset a64_resets[] = {
        [RST_BUS_OHCI0]         = RESET(0x2c0, BIT(28)),
        [RST_BUS_OHCI1]         = RESET(0x2c0, BIT(29)),
 
+       [RST_BUS_DE]            = RESET(0x2c4, BIT(12)),
+
        [RST_BUS_UART0]         = RESET(0x2d8, BIT(16)),
        [RST_BUS_UART1]         = RESET(0x2d8, BIT(17)),
        [RST_BUS_UART2]         = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index f81633b92d5a..bf8d963d18b6 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -30,6 +30,8 @@ static struct ccu_clk_gate h3_gates[] = {
        [CLK_BUS_OHCI2]         = GATE(0x060, BIT(30)),
        [CLK_BUS_OHCI3]         = GATE(0x060, BIT(31)),
 
+       [CLK_BUS_DE]            = GATE(0x064, BIT(12)),
+
        [CLK_BUS_UART0]         = GATE(0x06c, BIT(16)),
        [CLK_BUS_UART1]         = GATE(0x06c, BIT(17)),
        [CLK_BUS_UART2]         = GATE(0x06c, BIT(18)),
@@ -48,6 +50,8 @@ static struct ccu_clk_gate h3_gates[] = {
        [CLK_USB_OHCI1]         = GATE(0x0cc, BIT(17)),
        [CLK_USB_OHCI2]         = GATE(0x0cc, BIT(18)),
        [CLK_USB_OHCI3]         = GATE(0x0cc, BIT(19)),
+
+       [CLK_DE]                = GATE(0x104, BIT(31)),
 };
 
 static struct ccu_reset h3_resets[] = {
@@ -72,6 +76,8 @@ static struct ccu_reset h3_resets[] = {
        [RST_BUS_OHCI2]         = RESET(0x2c0, BIT(30)),
        [RST_BUS_OHCI3]         = RESET(0x2c0, BIT(31)),
 
+       [RST_BUS_DE]            = RESET(0x2c4, BIT(12)),
+
        [RST_BUS_EPHY]          = RESET(0x2c8, BIT(2)),
 
        [RST_BUS_UART0]         = RESET(0x2d8, BIT(16)),
-- 
2.30.1

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