Hi* Clement,* this week we have had no luck with *Allwinner A13* *video decoding*, here you can find my *device tree*. We have added *panel description* (before we used an uboot configuration) *front-end*, *back-end* and *tcon*. Also on linux mainline kernel (5.9.11) we have selected *DRM_SUN4I* and *DRM_SUN4I_BACKEND*, but seems to be *no DRM plane support* on our system (no *sun4i-drm* kernel messages and no */dev/dri/card0* device)
Also with *VLC player *we have selected in the menu the configuration options: *VA-API video decoder* and *X11 video output (XCB)* but no video decoding. With *MPV player* instead we can see some video frames, but it seems to be trying to decode via software, so it is almost like static pictures. Best Regards, *Sergio Sota* This device tree is based on mainline kernel *sun5i-a13-olinuxino-micro.dts* ####################################################### ################## DEVICE TREE START ##################### ####################################################### /* * Copyright 2012 Maxime Ripard <[email protected]> * Copyright 2013 Hans de Goede <[email protected]> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "sun5i-a13.dtsi" #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pwm/pwm.h> #include <dt-bindings/interrupt-controller/irq.h> / { model = "Olimex A13-Olinuxino Micro"; compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; aliases { serial0 = &uart1; }; chosen { stdout-path = "serial0:115200n8"; }; leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&led_pins_olinuxinom>; power { label = "a13-olinuxino-micro:green:power"; gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */ default-state = "on"; }; }; /***************************************************************************** * clock spi0 mcp2515 (spi can controller) *****************************************************************************/ clocks { #address-cells = <1>; #size-cells = <1>; can0_osc_fixed: can0_osc_fixed { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <10000000>; }; }; /***************************************************************************** * panel backlight *****************************************************************************/ backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; }; /***************************************************************************** * panel tft lcd 10.1" (rgb interface) *****************************************************************************/ panel { compatible = "olimex,lcd-olinuxino", "simple-panel"; power-supply = <®_vcc3v3>; enable-gpios = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ backlight = <&backlight>; status = "okay"; display-timings { timing0 { clock-frequency = <45000000>; hactive = <1024>; vactive = <600>; hfront-porch = <16>; hback-porch = <150>; hsync-len = <10>; vback-porch = <2>; vfront-porch = <21>; vsync-len = <2>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <1>; }; }; port { #address-cells = <1>; #size-cells = <0>; panel_input: endpoint { remote-endpoint = <&tcon0_out_lcd>; }; }; }; }; &ehci0 { status = "okay"; }; &i2c0 { status = "okay"; }; &i2c1 { status = "okay"; }; &i2c2 { status = "okay"; }; &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ status = "okay"; }; &ohci0 { status = "okay"; }; &otg_sram { status = "okay"; }; ®_usb0_vbus { gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ status = "okay"; }; ®_usb1_vbus { gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pg_pins>; status = "okay"; }; &usb_otg { dr_mode = "otg"; status = "okay"; }; &usbphy { usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; &pio { led_pins_olinuxinom: led-pin { pins = "PG9"; function = "gpio_out"; drive-strength = <20>; }; /***************************************************************************** * spi0 pins *****************************************************************************/ spi0_pins: spi0_pins { pins = "PC0", "PC1", "PC2"; function = "spi0"; }; spi0_cs0_pin: spi0_cs_pin { pins = "PC3"; function = "spi0"; }; /***************************************************************************** * spi2 ethernet controller (enc28j60) pins *****************************************************************************/ eth0_irq_pin: eth0_irq_pin { pins = "PB3"; function = "irq"; bias-pull-up; }; /***************************************************************************** * spi2 pins *****************************************************************************/ spi2_pins: spi2_pins { pins = "PE1", "PE2", "PE3"; function = "spi2"; }; spi2_cs0_pin: spi2_cs0_pin { pins = "PE0"; function = "spi2"; }; /***************************************************************************** * spi0 can controller (mcp2515) pins *****************************************************************************/ can0_irq_pin: can0_irq_pin { pins = "PB4"; function = "irq"; bias-pull-up; }; }; /***************************************************************************** * spi0 (mcp2515 spi can controller) *****************************************************************************/ &spi0 { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; status = "okay"; mcp2515@0 { compatible = "microchip,mcp2515"; reg = <0>; pinctrl-names = "default"; pinctrl-0 = <&can0_irq_pin>; interrupt-parent = <&pio>; interrupts = <1 4 2>; /* PB4 IRQ_TYPE_EDGE_FALLING */ clocks = <&can0_osc_fixed>; spi-max-frequency = <10000000>; status = "okay"; }; }; /***************************************************************************** * spi2 (enc28j60 spi ethernet controller) *****************************************************************************/ &spi2 { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi2_pins>, <&spi2_cs0_pin>; status = "okay"; enc28j60@0 { compatible = "microchip,enc28j60"; /* compatible = "microchip,encx24j600"; */ reg = <0>; pinctrl-names = "default"; pinctrl-0 = <ð0_irq_pin>; interrupt-parent = <&pio>; interrupts = <1 3 2>; /* PB3 IRQ_TYPE_EDGE_FALLING */ spi-max-frequency = <12000000>; status = "okay"; }; }; /***************************************************************************** * codec audio controller (headphones) *****************************************************************************/ &codec { status = "okay"; }; /***************************************************************************** * crypto engine (sha, md5, rng) *****************************************************************************/ &crypto { status = "okay"; }; /***************************************************************************** * front end (display engine) *****************************************************************************/ &fe0 { status = "okay"; }; /***************************************************************************** * back end (display engine) *****************************************************************************/ &be0 { status = "okay"; }; /***************************************************************************** * pipeline (display engine) *****************************************************************************/ &tcon0 { pinctrl-names = "default"; pinctrl-0 = <&lcd_rgb666_pins>; status = "okay"; }; /***************************************************************************** * timing controller (panel tft lcd 10.1") *****************************************************************************/ &tcon0_out { tcon0_out_lcd: endpoint@0 { reg = <0>; remote-endpoint = <&panel_input>; }; }; /***************************************************************************** * pwm controller *****************************************************************************/ &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; status = "okay"; }; ####################################################### ################### DEVICE TREE END ###################### ####################################################### El domingo, 6 de diciembre de 2020 a las 19:02:09 UTC+1, [email protected] escribió: > Hi Sergio, > > On Fri, 4 Dec 2020 at 13:31, Sergio Sota <[email protected]> wrote: > > > > Dear all, > > > > I'm building a linux system for the Olimex A13SOM module. This little > module comes > > with the Allwinner A13 SOC. In the past we have been using other modules > with the > > Allwinner A20 SOC and the old sunxi-linux kernel in order to have > support for all > > the SOC peripherals (as the Video Engine decoder, Mali GPU, etc) > > > > This time we would like to use a mainline kernel, taking into account > that by now > > almost all peripherals are supported in mainline. We have had luck > tunning device > > tree (as we were used to use .fex files) and by now we can have Ethernet > over SPI, > > Can interface over SPI, ALSA audio output, LCD RGB video output, Cryto > engine to > > generate fast entropy, OpenGL ES support (thanks to LIMA driver and > Mesa3d libs) > > and so on... but we would like also to have video decoding support. > > > > We have turned on the frontend, backend, video engine in the device > tree, build > > the kernel with Cedrus V4L M2M driver, libva_vl42_request and > v4l2_request_test. > > (and also set the CMA memory allocation, environment variables, etc) > > > > Using vainfo everything is ok, the linux driver-libva request part > works, but then > > we check with v4l2_request_test utility and it fails as there is no DRM > support on > > our system. We have on the system /dev/video0 and /dev/media0 but no > /dev/dri/card0 > > device (in fact we selected the linux sun4i-drm driver but no message > appers on the > > boot sequence regarding this, even when build as module it happens > nothing...) > > > > We have checked the Cedrus driver information and appears to be no > support for the > > DRM plane in A13 SOC (broken/missing) and as I understand that means > that part of > > the picture composing work should be done by software (and that's not > reliable) > > > > My question is: is there DRM plane support for A13 SOC? (as time goes on > I checked > > there has been work done in the mainline kernel and fixes made) Then, in > case of no > > support, are there plans to add this support in the future? and finally, > could we > > play video files without this DRM support? by what means? > > Sorry I can't help you a lot on this. > I don't know if the wiki is up to date for this. > But note that A13 is similar to R8 => C.H.I.P Computer. > All stuff you found on R8 will be the same for A13. > > Have a look at the R8 CHIP device-tree. > > https://elixir.bootlin.com/linux/latest/source/arch/arm/boot/dts/sun5i-r8-chip.dts > > And check that you have a correct TCON description in your dt. > If you can, post your device-tree. > And don't forget to reply if you make it works :) > > Regards, > Clement > > > > > > Thanks in advance for your help and your time, your team have made a > wonderful > > work. I also apologize for my poor English, and for writing this email > as maybe this is > > not the proper way to issue this questions, but didn't know other way > > > > Best Regards, > > Sergio Sota > > > > -- > > You received this message because you are subscribed to the Google > Groups "linux-sunxi" group. > > To unsubscribe from this group and stop receiving emails from it, send > an email to [email protected]. > > To view this discussion on the web, visit > https://groups.google.com/d/msgid/linux-sunxi/a6390bb5-69f1-47a7-864c-399109838857n%40googlegroups.com > . > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/565d70c3-b708-4216-83fd-ae37d42858e0n%40googlegroups.com.
