Hi all, I am trying to port my custom board from legacy kernel 3.4 to the mainline. I am using an LVDS display with a capacitive touchscreen and it works fine. For the test, i am currently running Armbian Debian Buster without Desktop environment because i need only one application on top of all. I additionally installed manually by apt-get X window and ratpoison window manager. Run firefox which is used for Javascript GUI interpretation, Cedar VE for encoding/decoding and DisplayEngine for showing the video on display on a particular place and particular size. On mainline, i recompiled Cedar VE instead of Cedrus because i already wrote all needed features for both Encoding/Decoding H264 and MJPEG for old legacy kernel and because encoding is not currently supported by Cedrus. Under legacy kernel i wrote my VideoEngine application and managed to get 4 simultaneous operation (Encode H264 and MJPEG and Decode H264 and MJPEG), all this works smoothly for a long time in legacy kernel 3.4 with any issue.
For mainline, i recompiled CedarVE from uboborov repo: https://github.com/uboborov/sunxi-cedar-mainline. I already tested CedarVE Encoder part but for Decoder i need to show video on my display on particular place with particular resolution. On old kernel, there was /dev/disp node which was used for showing video across firefox application in a particular window place or even in full screen. My question is how to do this in Mainline kernel? I set my dtb and enable Display Engine but i am stuck there. I see in dmesg that framebuffer is switched from simple to sun4i-drm-fb and i have /dev/dri/card0 device node but i am not sure what is my next step. Do i need to create some drm plane for that purpose and how? Is there any simple example of how to do this? Also when i run '$startx ratpoison' in its output i can see next message: 'failed to load driver: sun4i-drm'. Does it mean that X window could not use DRM or what? I am not sure if drm is working or not. And did i create drm display engine pipeline as well? Also, i think that firefox which i am using for running my Javascript GUI is an overkill a little bit. Does someone else can recommend some other interpreter? Do i need to compile and run lima driver for my purpose? Sorry for long description. I also attached my dtb files and dmesg output here. Thanks, Milos Ladicorbic -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/afa43aef-bd6e-43b5-bf94-de6ce1555b72o%40googlegroups.com.
root@olinuxino:~# dmesg [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 5.8.0-rc1-g05ba036ff (milos@debian1064) (arm-linux-gnueabihf-gcc (Debian 8.3.0-2) 8.3.0, GNU ld (GNU Binutils for Debian) 2.31.1) #60 SMP Thu Jul 30 17:47:50 CEST 2020 [ 0.000000] CPU: ARMv7 Processor [410fc074] revision 4 (ARMv7), cr=10c5387d [ 0.000000] CPU: div instructions available: patching division code [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] OF: fdt: Machine model: sun7i-a20-tcs-7Zoll [ 0.000000] printk: bootconsole [earlycon0] enabled [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] Reserved memory: created CMA memory pool at 0x4a000000, size 96 MiB [ 0.000000] OF: reserved mem: initialized node default-pool, compatible id shared-dma-pool [ 0.000000] Zone ranges: [ 0.000000] Normal [mem 0x0000000040000000-0x000000005fda7fff] [ 0.000000] HighMem empty [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000040000000-0x000000005fda7fff] [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000005fda7fff] [ 0.000000] On node 0 totalpages: 130472 [ 0.000000] Normal zone: 1020 pages used for memmap [ 0.000000] Normal zone: 0 pages reserved [ 0.000000] Normal zone: 130472 pages, LIFO batch:31 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: Using PSCI v0.1 Function IDs from DT [ 0.000000] percpu: Embedded 15 pages/cpu s30732 r8192 d22516 u61440 [ 0.000000] pcpu-alloc: s30732 r8192 d22516 u61440 alloc=15*4096 [ 0.000000] pcpu-alloc: [0] 0 [0] 1 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 129452 [ 0.000000] Kernel command line: console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p5 rootfstype=ext4 rootwait panic=10 rw [ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear) [ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear) [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off [ 0.000000] Memory: 406620K/521888K available (7168K kernel code, 497K rwdata, 1932K rodata, 1024K init, 246K bss, 16964K reserved, 98304K cma-reserved, 0K highmem) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 [ 0.000000] rcu: Hierarchical RCU implementation. [ 0.000000] rcu: RCU event tracing is enabled. [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 [ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16 [ 0.000000] GIC: Using split EOI/Deactivate mode [ 0.000000] random: get_random_bytes called from start_kernel+0x308/0x494 with crng_init=0 [ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys). [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns [ 0.000008] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns [ 0.008002] Switching to timer-based delay loop, resolution 41ns [ 0.014437] clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns [ 0.023889] clocksource: hstimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 6370868154 ns [ 0.033462] Console: colour dummy device 80x30 [ 0.037949] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000) [ 0.048311] pid_max: default: 32768 minimum: 301 [ 0.053102] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.060427] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.069015] CPU: Testing write buffer coherency: ok [ 0.074351] /cpus/cpu@0 missing clock-frequency property [ 0.079674] /cpus/cpu@1 missing clock-frequency property [ 0.085029] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.091380] Setting up static identity map for 0x40100000 - 0x40100060 [ 0.098129] rcu: Hierarchical SRCU implementation. [ 0.103614] smp: Bringing up secondary CPUs ... [ 0.119134] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 [ 0.119313] smp: Brought up 1 node, 2 CPUs [ 0.129097] SMP: Total of 2 processors activated (96.00 BogoMIPS). [ 0.135268] CPU: All CPU(s) started in HYP mode. [ 0.139890] CPU: Virtualization extensions available. [ 0.145774] devtmpfs: initialized [ 0.156434] VFP support v0.3: implementor 41 architecture 2 part 30 variant 7 rev 4 [ 0.164482] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns [ 0.174361] futex hash table entries: 512 (order: 3, 32768 bytes, linear) [ 0.184990] pinctrl core: initialized pinctrl subsystem [ 0.190975] thermal_sys: Registered thermal governor 'step_wise' [ 0.191906] NET: Registered protocol family 16 [ 0.204137] DMA: preallocated 256 KiB pool for atomic coherent allocations [ 0.212383] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers. [ 0.220380] hw-breakpoint: maximum watchpoint size is 8 bytes. [ 0.249860] cam: supplied by vcc5v0 [ 0.253755] cam-avdd: supplied by cam [ 0.257831] cam-dvdd: supplied by cam [ 0.261896] cam-dovdd: supplied by cam [ 0.266617] SCSI subsystem initialized [ 0.270929] libata version 3.00 loaded. [ 0.271193] usbcore: registered new interface driver usbfs [ 0.276734] usbcore: registered new interface driver hub [ 0.282212] usbcore: registered new device driver usb [ 0.287594] mc: Linux media interface: v0.10 [ 0.291895] videodev: Linux video capture interface: v2.00 [ 0.297464] pps_core: LinuxPPS API ver. 1 registered [ 0.302433] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <[email protected]> [ 0.311582] PTP clock support registered [ 0.315803] Advanced Linux Sound Architecture Driver Initialized. [ 0.323173] clocksource: Switched to clocksource arch_sys_counter [ 0.330364] simple-framebuffer chosen:framebuffer-lcd0-hdmi: Can't parse width property [ 0.338502] simple-framebuffer: probe of chosen:framebuffer-lcd0-hdmi failed with error -22 [ 0.347511] simple-framebuffer 5fda8000.framebuffer: framebuffer at 0x5fda8000, 0x258000 bytes, mapped to 0x(ptrval) [ 0.358061] simple-framebuffer 5fda8000.framebuffer: format=x8r8g8b8, mode=1024x600x32, linelength=4096 [ 0.378787] Console: switching to colour frame buffer device 128x37 [ 0.394553] simple-framebuffer 5fda8000.framebuffer: fb0: simplefb registered! [ 0.402366] simple-framebuffer chosen:framebuffer-lcd0-tve0: Can't parse width property [ 0.410426] simple-framebuffer: probe of chosen:framebuffer-lcd0-tve0 failed with error -22 [ 0.427734] NET: Registered protocol family 2 [ 0.432736] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear) [ 0.441195] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear) [ 0.448996] TCP bind hash table entries: 4096 (order: 3, 32768 bytes, linear) [ 0.456199] TCP: Hash tables configured (established 4096 bind 4096) [ 0.462711] UDP hash table entries: 256 (order: 1, 8192 bytes, linear) [ 0.469319] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear) [ 0.476539] NET: Registered protocol family 1 [ 0.481735] RPC: Registered named UNIX socket transport module. [ 0.487768] RPC: Registered udp transport module. [ 0.492465] RPC: Registered tcp transport module. [ 0.497187] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 0.504395] hw perfevents: no interrupt-affinity property for /pmu, guessing. [ 0.511812] hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available [ 0.521755] workingset: timestamp_bits=30 max_order=17 bucket_order=0 [ 0.535273] NFS: Registering the id_resolver key type [ 0.540376] Key type id_resolver registered [ 0.544643] Key type id_legacy registered [ 0.548775] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247) [ 0.556211] io scheduler mq-deadline registered [ 0.560735] io scheduler kyber registered [ 0.566029] sun4i-usb-phy 1c13400.phy: Couldn't get regulator usb0_vbus... Deferring probe [ 0.578402] sun4i-pinctrl 1c20800.pinctrl: initialized sunXi PIO driver [ 0.587424] sun4i-pinctrl 1c20800.pinctrl: supply vcc-ph not found, using dummy regulator [ 0.661278] Serial: 8250/16550 driver, 8 ports, IRQ sharing disabled [ 0.670095] sun4i-pinctrl 1c20800.pinctrl: supply vcc-pb not found, using dummy regulator [ 0.679446] printk: console [ttyS0] disabled [ 0.703962] 1c28000.serial: ttyS0 at MMIO 0x1c28000 (irq = 49, base_baud = 1500000) is a U6_16550A [ 0.713001] printk: console [ttyS0] enabled [ 0.721379] printk: bootconsole [earlycon0] disabled [ 0.731884] sun4i-pinctrl 1c20800.pinctrl: supply vcc-pi not found, using dummy regulator [ 0.763236] 1c29800.serial: ttyS1 at MMIO 0x1c29800 (irq = 50, base_baud = 1500000) is a U6_16550A [ 0.793764] 1c29c00.serial: ttyS2 at MMIO 0x1c29c00 (irq = 51, base_baud = 1500000) is a U6_16550A [ 0.806084] sun4i-pinctrl 1c20800.pinctrl: supply vcc-pd not found, using dummy regulator [ 0.824733] libphy: Fixed MDIO Bus: probed [ 0.829208] CAN device driver interface [ 0.834091] sun7i-dwmac 1c50000.ethernet: IRQ eth_wake_irq not found [ 0.840451] sun7i-dwmac 1c50000.ethernet: IRQ eth_lpi not found [ 0.846547] sun7i-dwmac 1c50000.ethernet: PTP uses main clock [ 0.852299] sun7i-dwmac 1c50000.ethernet: no reset control found [ 0.858387] sun7i-dwmac 1c50000.ethernet: no regulator found [ 0.864386] sun7i-dwmac 1c50000.ethernet: Version ID not available [ 0.870577] sun7i-dwmac 1c50000.ethernet: DWMAC1000 [ 0.875614] sun7i-dwmac 1c50000.ethernet: DMA HW capability register supported [ 0.882832] sun7i-dwmac 1c50000.ethernet: Normal descriptors [ 0.888537] sun7i-dwmac 1c50000.ethernet: Ring mode enabled [ 0.894739] libphy: stmmac: probed [ 0.900824] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 0.907451] ehci-platform: EHCI generic platform driver [ 0.913304] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver [ 0.919518] ohci-platform: OHCI generic platform driver [ 0.927569] sunxi-rtc 1c20d00.rtc: registered as rtc0 [ 0.932675] sunxi-rtc 1c20d00.rtc: setting system clock to 1970-01-01T00:00:18 UTC (18) [ 0.940911] i2c /dev entries driver [ 0.945764] axp20x-i2c 0-0034: AXP20x variant AXP209 found [ 0.958716] input: axp20x-pek as /devices/platform/soc/1c2ac00.i2c/i2c-0/0-0034/axp20x-pek/input/input0 [ 0.977744] ldo1: supplied by regulator-dummy [ 0.982504] ldo2: supplied by regulator-dummy [ 0.988079] ldo3: supplied by regulator-dummy [ 0.993235] ldo4: supplied by regulator-dummy [ 0.997653] pg: Bringing 3000000uV into 2800000-2800000uV [ 1.003668] ldo5: supplied by regulator-dummy [ 1.008741] dcdc2: supplied by regulator-dummy [ 1.013986] dcdc3: supplied by regulator-dummy [ 1.020425] axp20x-i2c 0-0034: AXP20X driver loaded [ 1.027583] Goodix-TS 2-005d: supply AVDD28 not found, using dummy regulator [ 1.034873] Goodix-TS 2-005d: supply VDDIO not found, using dummy regulator [ 1.154654] Goodix-TS 2-005d: ID 911, version: 1060 [ 1.160671] axp20x-usb-power-supply axp20x-usb-power-supply: DMA mask not set [ 1.168114] Goodix-TS 2-005d: Direct firmware load for goodix_911_cfg.bin failed with error -2 [ 1.177123] random: fast init done [ 1.181369] axp20x-ac-power-supply axp20x-ac-power-supply: DMA mask not set [ 1.189554] sunxi-wdt 1c20c90.watchdog: Watchdog enabled (timeout=16 sec, nowayout=0) [ 1.203056] sunxi-mmc 1c0f000.mmc: Got CD GPIO [ 1.217426] input: Goodix Capacitive TouchScreen as /devices/platform/soc/1c2b400.i2c/i2c-2/2-005d/input/input1 [ 1.240268] sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB [ 1.248720] sunxi-mmc 1c11000.mmc: allocated mmc-pwrseq [ 1.279386] sunxi-mmc 1c11000.mmc: initialized, max. request size: 16384 KB [ 1.287384] sun4i-ss 1c15000.crypto-engine: Die ID 0 [ 1.295182] usbcore: registered new interface driver usbhid [ 1.300762] usbhid: USB HID core driver [ 1.304923] axp20x-adc axp20x-adc: DMA mask not set [ 1.314993] debugfs: Directory '1c22c00.codec' with parent 'sun4i-codec' already present! [ 1.325062] sun4i-codec 1c22c00.codec: Codec <-> 1c22c00.codec mapping ok [ 1.333904] NET: Registered protocol family 17 [ 1.338395] can: controller area network core (rev 20170425 abi 9) [ 1.344755] NET: Registered protocol family 29 [ 1.349204] can: raw protocol (rev 20170425) [ 1.353499] can: broadcast manager protocol (rev 20170425 t) [ 1.359158] can: netlink gateway (rev 20190810) max_hops=1 [ 1.364948] Key type dns_resolver registered [ 1.369366] Registering SWP/SWPB emulation handler [ 1.391660] sun4i-pinctrl 1c20800.pinctrl: supply vcc-pd not found, using dummy regulator [ 1.402061] ehci-platform 1c14000.usb: EHCI Host Controller [ 1.407756] ehci-platform 1c14000.usb: new USB bus registered, assigned bus number 1 [ 1.416302] ehci-platform 1c14000.usb: irq 34, io mem 0x01c14000 [ 1.443152] ehci-platform 1c14000.usb: USB 2.0 started, EHCI 1.00 [ 1.450300] hub 1-0:1.0: USB hub found [ 1.454221] hub 1-0:1.0: 1 port detected [ 1.459472] ehci-platform 1c1c000.usb: EHCI Host Controller [ 1.465158] ehci-platform 1c1c000.usb: new USB bus registered, assigned bus number 2 [ 1.473452] ehci-platform 1c1c000.usb: irq 38, io mem 0x01c1c000 [ 1.503156] ehci-platform 1c1c000.usb: USB 2.0 started, EHCI 1.00 [ 1.510349] hub 2-0:1.0: USB hub found [ 1.514259] hub 2-0:1.0: 1 port detected [ 1.519427] ohci-platform 1c14400.usb: Generic Platform OHCI controller [ 1.526168] ohci-platform 1c14400.usb: new USB bus registered, assigned bus number 3 [ 1.534308] ohci-platform 1c14400.usb: irq 35, io mem 0x01c14400 [ 1.545174] mmc1: new DDR MMC card at address 0001 [ 1.551090] mmcblk1: mmc1:0001 P1XXXX 3.60 GiB [ 1.556380] mmcblk1boot0: mmc1:0001 P1XXXX partition 1 16.0 MiB [ 1.562923] mmcblk1boot1: mmc1:0001 P1XXXX partition 2 16.0 MiB [ 1.575117] mmcblk1: p1 p2 p3 p4 < p5 p6 p7 p8 > [ 1.608227] hub 3-0:1.0: USB hub found [ 1.612070] hub 3-0:1.0: 1 port detected [ 1.617361] ohci-platform 1c1c400.usb: Generic Platform OHCI controller [ 1.624086] ohci-platform 1c1c400.usb: new USB bus registered, assigned bus number 4 [ 1.632717] ohci-platform 1c1c400.usb: irq 39, io mem 0x01c1c400 [ 1.708159] hub 4-0:1.0: USB hub found [ 1.711978] hub 4-0:1.0: 1 port detected [ 1.717318] usb_phy_generic usb_phy_generic.0.auto: supply vcc not found, using dummy regulator [ 1.727195] musb-hdrc musb-hdrc.1.auto: MUSB HDRC host driver [ 1.732971] musb-hdrc musb-hdrc.1.auto: new USB bus registered, assigned bus number 5 [ 1.742133] hub 5-0:1.0: USB hub found [ 1.746023] hub 5-0:1.0: 1 port detected [ 1.777047] sun4i-pinctrl 1c20800.pinctrl: supply vcc-pd not found, using dummy regulator [ 1.786012] sun4i-drm display-engine: bound 1e00000.display-frontend (ops 0xc084efa0) [ 1.794053] sun4i-drm display-engine: bound 1e20000.display-frontend (ops 0xc084efa0) [ 1.802329] sun4i-drm display-engine: bound 1e60000.display-backend (ops 0xc084e7e4) [ 1.810490] sun4i-drm display-engine: bound 1e40000.display-backend (ops 0xc084e7e4) [ 1.818915] sun4i-drm display-engine: bound 1c0c000.lcd-controller (ops 0xc084d344) [ 1.827207] sun4i-drm display-engine: No panel or bridge found... RGB output disabled [ 1.835114] sun4i-drm display-engine: bound 1c0d000.lcd-controller (ops 0xc084d344) [ 1.842769] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 1.849405] checking generic (5fda8000 258000) vs hw (0 ffffffff) [ 1.849411] fb0: switching to sun4i-drm-fb from simple [ 1.855760] Console: switching to colour dummy device 80x30 [ 1.862260] [drm] Initialized sun4i-drm 1.0.0 20150629 for display-engine on minor 0 [ 1.916430] Console: switching to colour frame buffer device 128x37 [ 1.938754] sun4i-drm display-engine: fb0: sun4i-drmdrmfb frame buffer device [ 1.946529] ALSA device list: [ 1.949507] #0: sun4i-codec [ 2.399395] EXT4-fs (mmcblk1p5): recovery complete [ 2.405049] EXT4-fs (mmcblk1p5): mounted filesystem with ordered data mode. Opts: (null) [ 2.413277] VFS: Mounted root (ext4 filesystem) on device 179:5. [ 2.420007] devtmpfs: mounted [ 2.424386] Freeing unused kernel memory: 1024K [ 2.429111] Run /sbin/init as init process [ 2.433241] with arguments: [ 2.433245] /sbin/init [ 2.433247] with environment: [ 2.433249] HOME=/ [ 2.433252] TERM=linux [ 2.822632] systemd[1]: System time before build time, advancing clock. [ 2.831455] systemd[1]: Failed to find module 'autofs4' [ 2.861721] systemd[1]: systemd 241 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN2 +IDN -PCRE2 default-hierarchy=hybrid) [ 2.883939] systemd[1]: Detected architecture arm. [ 2.928933] systemd[1]: Set hostname to <olinuxino>. [ 2.939231] systemd[1]: Failed to bump fs.file-max, ignoring: Invalid argument [ 3.371220] systemd-sysv-generator[83]: Overwriting existing symlink /run/systemd/generator.late/cpufrequtils.service with real service. [ 3.405695] systemd[1]: File /lib/systemd/system/systemd-journald.service:12 configures an IP firewall (IPAddressDeny=any), but the local system does not support BPF/cgroup based firewalling. [ 3.422883] systemd[1]: Proceeding WITHOUT firewalling in effect! (This warning is only shown for the first loaded unit using IP firewalling.) [ 3.817381] random: systemd: uninitialized urandom read (16 bytes read) [ 3.838757] random: systemd: uninitialized urandom read (16 bytes read) [ 3.845697] systemd[1]: Reached target System Time Synchronized. [ 3.883464] random: systemd: uninitialized urandom read (16 bytes read) [ 3.891190] systemd[1]: Created slice User and Session Slice. [ 3.924168] systemd[1]: Listening on udev Kernel Socket. [ 3.954497] systemd[1]: Created slice system-serial\x2dgetty.slice. [ 5.947112] systemd-journald[107]: Received request to flush runtime journal from PID 1 [ 6.308666] sunxi_cedar_ve: module is from the staging directory, the quality is unknown, you have been warned. [ 6.309954] sunxi cedar version 0.1 [ 6.310191] [cedar]: install start!!! [ 6.310315] cedar_ve: cedar-ve the get irq is 30 [ 6.310344] sunxi-cedar 1c0e000.video-engine: assigned reserved memory node default-pool [ 6.416982] [cedar]: memory allocated at address 4A500000 [ 6.416997] [cedar]: install end!!! [ 6.852333] sun4i-csi 1c1d000.csi: Device registered as video0 [ 12.745776] EXT4-fs (mmcblk1p7): mounted filesystem with ordered data mode. Opts: (null) [ 15.098997] random: crng init done [ 15.099020] random: 7 urandom warning(s) missed due to ratelimiting [ 21.831783] sun7i-dwmac 1c50000.ethernet eth0: PHY [stmmac-0:01] driver [Generic PHY] (irq=POLL) [ 21.833910] sun7i-dwmac 1c50000.ethernet eth0: No Safety Features support found [ 21.833930] sun7i-dwmac 1c50000.ethernet eth0: RX IPC Checksum Offload disabled [ 21.833944] sun7i-dwmac 1c50000.ethernet eth0: No MAC Management Counters available [ 21.833954] sun7i-dwmac 1c50000.ethernet eth0: PTP not supported by HW [ 21.833973] sun7i-dwmac 1c50000.ethernet eth0: configuring for phy/mii link mode [ 23.903856] sun7i-dwmac 1c50000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx [ 32.543211] vcc3v0: disabling [ 32.543231] cam-avdd: disabling [ 32.543237] cam-dvdd: disabling [ 32.543242] cam-dovdd: disabling root@olinuxino:~#
/* * Copyright 2013 Maxime Ripard * * Maxime Ripard <[email protected]> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/dma/sun4i-a10.h> #include <dt-bindings/clock/sun7i-a20-ccu.h> #include <dt-bindings/reset/sun4i-a10-ccu.h> #include <dt-bindings/pinctrl/sun4i-a10.h> / { interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; aliases { ethernet0 = &gmac; }; chosen { #address-cells = <1>; #size-cells = <1>; ranges; framebuffer-lcd0-hdmi { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>, <&ccu CLK_HDMI>; status = "disabled"; }; framebuffer-lcd0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; framebuffer-lcd0-tve0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; clocks = <&ccu CLK_CPU>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < /* kHz uV */ 960000 1400000 912000 1400000 864000 1300000 720000 1200000 528000 1100000 312000 1000000 144000 1000000 >; #cooling-cells = <2>; }; cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; clocks = <&ccu CLK_CPU>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < /* kHz uV */ 960000 1400000 912000 1400000 864000 1300000 720000 1200000 528000 1100000 312000 1000000 144000 1000000 >; #cooling-cells = <2>; }; }; thermal-zones { cpu_thermal { /* milliseconds */ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&rtp>; cooling-maps { map0 { trip = <&cpu_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { cpu_alert0: cpu_alert0 { /* milliCelsius */ temperature = <75000>; hysteresis = <2000>; type = "passive"; }; cpu_crit: cpu_crit { /* milliCelsius */ temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; }; }; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ cma_pool: default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; reusable; linux,cma-default; }; }; timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; pmu { compatible = "arm,cortex-a7-pmu"; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; }; clocks { #address-cells = <1>; #size-cells = <1>; ranges; osc24M: clk-24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; osc32k: clk-32k { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; clock-output-names = "osc32k"; }; /* * The following two are dummy clocks, placeholders * used in the gmac_tx clock. The gmac driver will * choose one parent depending on the PHY interface * mode, using clk_set_rate auto-reparenting. * * The actual TX clock rate is not controlled by the * gmac_tx clock. */ mii_phy_tx_clk: clk-mii-phy-tx { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; clock-output-names = "mii_phy_tx"; }; gmac_int_tx_clk: clk-gmac-int-tx { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <125000000>; clock-output-names = "gmac_int_tx"; }; gmac_tx_clk: clk@1c20164 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-gmac-clk"; reg = <0x01c20164 0x4>; clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; clock-output-names = "gmac_tx"; }; }; de: display-engine { compatible = "allwinner,sun7i-a20-display-engine"; allwinner,pipelines = <&fe0>, <&fe1>; status = "disabled"; }; soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; syscon: system-control@1c00000 { compatible = "allwinner,sun7i-a20-system-control", "allwinner,sun4i-a10-system-control", "syscon"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; ranges; sram_a: sram@0 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00000000 0xc000>; emac_sram: sram-section@8000 { compatible = "allwinner,sun7i-a20-sram-a3-a4", "allwinner,sun4i-a10-sram-a3-a4"; reg = <0x8000 0x4000>; status = "disabled"; }; }; sram_d: sram@10000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; otg_sram: sram-section@0 { compatible = "allwinner,sun7i-a20-sram-d", "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; }; }; sram_c: sram@1d00000 { compatible = "mmio-sram"; reg = <0x01d00000 0xd0000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x01d00000 0xd0000>; ve_sram: sram-section@0 { compatible = "allwinner,sun7i-a20-sram-c1", "allwinner,sun4i-a10-sram-c1"; reg = <0x000000 0x80000>; }; }; }; nmi_intc: interrupt-controller@1c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; #interrupt-cells = <2>; reg = <0x01c00030 0x0c>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_DMA>; #dma-cells = <2>; }; nfc: nand-controller@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 3>; dma-names = "rxtx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; spi0: spi@1c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 27>, <&dma SUN4I_DMA_DEDICATED 26>; dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; num-cs = <4>; }; spi1: spi@1c06000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 9>, <&dma SUN4I_DMA_DEDICATED 8>; dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; num-cs = <1>; }; csi0: csi@1c09000 { compatible = "allwinner,sun7i-a20-csi0"; reg = <0x01c09000 0x1000>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; clock-names = "bus", "isp", "ram"; resets = <&ccu RST_CSI0>; status = "disabled"; }; emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_EMAC>; allwinner,sram = <&emac_sram 1>; status = "disabled"; }; mdio: mdio@1c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x01c0b080 0x14>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun7i-a20-tcon0", "allwinner,sun7i-a20-tcon"; reg = <0x01c0c000 0x1000>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>; reset-names = "lcd", "lvds"; clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_TCON0_CH0>, <&ccu CLK_TCON0_CH1>; clock-names = "ahb", "tcon-ch0", "tcon-ch1"; clock-output-names = "tcon0-pixel-clock"; #clock-cells = <0>; dmas = <&dma SUN4I_DMA_DEDICATED 14>; ports { #address-cells = <1>; #size-cells = <0>; tcon0_in: port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; tcon0_in_be0: endpoint@0 { reg = <0>; remote-endpoint = <&be0_out_tcon0>; }; tcon0_in_be1: endpoint@1 { reg = <1>; remote-endpoint = <&be1_out_tcon0>; }; }; tcon0_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; tcon0_out_hdmi: endpoint@1 { reg = <1>; remote-endpoint = <&hdmi_in_tcon0>; allwinner,tcon-channel = <1>; }; }; }; }; tcon1: lcd-controller@1c0d000 { compatible = "allwinner,sun7i-a20-tcon1", "allwinner,sun7i-a20-tcon"; reg = <0x01c0d000 0x1000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; resets = <&ccu RST_TCON1>; reset-names = "lcd"; clocks = <&ccu CLK_AHB_LCD1>, <&ccu CLK_TCON1_CH0>, <&ccu CLK_TCON1_CH1>; clock-names = "ahb", "tcon-ch0", "tcon-ch1"; clock-output-names = "tcon1-pixel-clock"; #clock-cells = <0>; dmas = <&dma SUN4I_DMA_DEDICATED 15>; ports { #address-cells = <1>; #size-cells = <0>; tcon1_in: port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; tcon1_in_be0: endpoint@0 { reg = <0>; remote-endpoint = <&be0_out_tcon1>; }; tcon1_in_be1: endpoint@1 { reg = <1>; remote-endpoint = <&be1_out_tcon1>; }; }; tcon1_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; tcon1_out_hdmi: endpoint@1 { reg = <1>; remote-endpoint = <&hdmi_in_tcon1>; allwinner,tcon-channel = <1>; }; }; }; }; /* video-codec@1c0e000 { compatible = "allwinner,sun7i-a20-video-engine"; reg = <0x01c0e000 0x1000>; clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, <&ccu CLK_DRAM_VE>; clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_VE>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; allwinner,sram = <&ve_sram 1>; }; */ ve: video-engine@01c0e000 { compatible = "allwinner,sunxi-cedar-ve"; reg = <0x01c0e000 0x1000>, <0x01c00000 0x10>, <0x01c20000 0x800>; memory-region = <&cma_pool>; syscon = <&syscon>; clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, <&ccu CLK_DRAM_VE>; clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_VE>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; allwinner,sram = <&ve_sram 1>; }; mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>, <&ccu CLK_MMC0_OUTPUT>, <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; mmc1: mmc@1c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>, <&ccu CLK_MMC1_OUTPUT>, <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; mmc2: mmc@1c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>, <&ccu CLK_MMC2_OUTPUT>, <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; mmc3: mmc@1c12000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c12000 0x1000>; clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>, <&ccu CLK_MMC3_OUTPUT>, <&ccu CLK_MMC3_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; usb_otg: usb@1c13000 { compatible = "allwinner,sun4i-a10-musb"; reg = <0x01c13000 0x0400>; clocks = <&ccu CLK_AHB_OTG>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mc"; phys = <&usbphy 0>; phy-names = "usb"; extcon = <&usbphy 0>; allwinner,sram = <&otg_sram 1>; dr_mode = "otg"; status = "disabled"; }; usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun7i-a20-usb-phy"; reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; reg-names = "phy_ctrl", "pmu1", "pmu2"; clocks = <&ccu CLK_USB_PHY>; clock-names = "usb_phy"; resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>, <&ccu RST_USB_PHY2>; reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; status = "disabled"; }; ehci0: usb@1c14000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_EHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; ohci0: usb@1c14400 { compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; crypto: crypto-engine@1c15000 { compatible = "allwinner,sun7i-a20-crypto", "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; }; hdmi: hdmi@1c16000 { compatible = "allwinner,sun7i-a20-hdmi", "allwinner,sun5i-a10s-hdmi"; reg = <0x01c16000 0x1000>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, <&ccu CLK_PLL_VIDEO0_2X>, <&ccu CLK_PLL_VIDEO1_2X>; clock-names = "ahb", "mod", "pll-0", "pll-1"; dmas = <&dma SUN4I_DMA_NORMAL 16>, <&dma SUN4I_DMA_NORMAL 16>, <&dma SUN4I_DMA_DEDICATED 24>; dma-names = "ddc-tx", "ddc-rx", "audio-tx"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; hdmi_in: port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; hdmi_in_tcon0: endpoint@0 { reg = <0>; remote-endpoint = <&tcon0_out_hdmi>; }; hdmi_in_tcon1: endpoint@1 { reg = <1>; remote-endpoint = <&tcon1_out_hdmi>; }; }; hdmi_out: port@1 { reg = <1>; }; }; }; spi2: spi@1c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 29>, <&dma SUN4I_DMA_DEDICATED 28>; dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; num-cs = <1>; }; ahci: sata@1c18000 { compatible = "allwinner,sun4i-a10-ahci"; reg = <0x01c18000 0x1000>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; status = "disabled"; }; ehci1: usb@1c1c000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c1c000 0x100>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_EHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; ohci1: usb@1c1c400 { compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; csi1: csi@1c1d000 { compatible = "allwinner,sun7i-a20-csi1", "allwinner,sun4i-a10-csi1"; reg = <0x01c1d000 0x1000>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; clock-names = "bus", "ram"; resets = <&ccu RST_CSI1>; status = "disabled"; }; spi3: spi@1c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 31>, <&dma SUN4I_DMA_DEDICATED 30>; dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; num-cs = <1>; }; ccu: clock@1c20000 { compatible = "allwinner,sun7i-a20-ccu"; reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; }; pio: pinctrl@1c20800 { compatible = "allwinner,sun7i-a20-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; #gpio-cells = <3>; /omit-if-no-ref/ can_pa_pins: can-pa-pins { pins = "PA16", "PA17"; function = "can"; }; /omit-if-no-ref/ can_ph_pins: can-ph-pins { pins = "PH20", "PH21"; function = "can"; }; /omit-if-no-ref/ clk_out_a_pin: clk-out-a-pin { pins = "PI12"; function = "clk_out_a"; }; /omit-if-no-ref/ clk_out_b_pin: clk-out-b-pin { pins = "PI13"; function = "clk_out_b"; }; /omit-if-no-ref/ csi0_8bits_pins: csi-8bits-pins { pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11"; function = "csi0"; }; /omit-if-no-ref/ csi0_clk_pin: csi-clk-pin { pins = "PE1"; function = "csi0"; }; /omit-if-no-ref/ csi1_8bits_pg_pins: csi1-8bits-pg-pins { pins = "PG0", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7", "PG8", "PG9", "PG10", "PG11"; function = "csi1"; }; /omit-if-no-ref/ csi1_8bits_ph_pins: csi1-8bits-ph-pins { pins = "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", "PH24", "PH26", "PH27"; function = "csi1"; }; /omit-if-no-ref/ csi1_24bits_ph_pins: csi1-24bits-ph-pins { pins = "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", "PH8", "PH9", "PH10", "PH11", "PH12", "PH13", "PH14", "PH15", "PH16", "PH17", "PH18", "PH19", "PH20", "PH21", "PH22", "PH23", "PH24", "PH25", "PH26", "PH27"; function = "csi1"; }; /omit-if-no-ref/ csi1_clk_pg_pin: csi1-clk-pg-pin { pins = "PG1"; function = "csi1"; }; /omit-if-no-ref/ emac_pa_pins: emac-pa-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15", "PA16"; function = "emac"; }; /omit-if-no-ref/ emac_ph_pins: emac-ph-pins { pins = "PH8", "PH9", "PH10", "PH11", "PH14", "PH15", "PH16", "PH17", "PH18", "PH19", "PH20", "PH21", "PH22", "PH23", "PH24", "PH25", "PH26"; function = "emac"; }; /omit-if-no-ref/ gmac_mii_pins: gmac-mii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15", "PA16"; function = "gmac"; }; /omit-if-no-ref/ gmac_rgmii_pins: gmac-rgmii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA10", "PA11", "PA12", "PA13", "PA15", "PA16"; function = "gmac"; /* * data lines in RGMII mode use DDR mode * and need a higher signal drive strength */ drive-strength = <40>; }; /omit-if-no-ref/ i2c0_pins: i2c0-pins { pins = "PB0", "PB1"; function = "i2c0"; }; /omit-if-no-ref/ i2c1_pins: i2c1-pins { pins = "PB18", "PB19"; function = "i2c1"; }; /omit-if-no-ref/ i2c2_pins: i2c2-pins { pins = "PB20", "PB21"; function = "i2c2"; }; /omit-if-no-ref/ i2c3_pins: i2c3-pins { pins = "PI0", "PI1"; function = "i2c3"; }; /omit-if-no-ref/ ir0_rx_pin: ir0-rx-pin { pins = "PB4"; function = "ir0"; }; /omit-if-no-ref/ ir0_tx_pin: ir0-tx-pin { pins = "PB3"; function = "ir0"; }; /omit-if-no-ref/ ir1_rx_pin: ir1-rx-pin { pins = "PB23"; function = "ir1"; }; /omit-if-no-ref/ ir1_tx_pin: ir1-tx-pin { pins = "PB22"; function = "ir1"; }; /omit-if-no-ref/ lcd_lvds0_pins: lcd-lvds0-pins { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9"; function = "lvds0"; }; /omit-if-no-ref/ lcd_lvds1_pins: lcd-lvds1-pins { pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19"; function = "lvds1"; }; /omit-if-no-ref/ mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; drive-strength = <30>; bias-pull-up; }; /omit-if-no-ref/ mmc2_pins: mmc2-pins { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11"; function = "mmc2"; drive-strength = <30>; bias-pull-up; }; /omit-if-no-ref/ mmc3_pins: mmc3-pins { pins = "PI4", "PI5", "PI6", "PI7", "PI8", "PI9"; function = "mmc3"; drive-strength = <30>; bias-pull-up; }; /omit-if-no-ref/ ps2_0_pins: ps2-0-pins { pins = "PI20", "PI21"; function = "ps2"; }; /omit-if-no-ref/ ps2_1_ph_pins: ps2-1-ph-pins { pins = "PH12", "PH13"; function = "ps2"; }; /omit-if-no-ref/ pwm0_pin: pwm0-pin { pins = "PB2"; function = "pwm"; }; /omit-if-no-ref/ pwm1_pin: pwm1-pin { pins = "PI3"; function = "pwm"; }; /omit-if-no-ref/ spdif_tx_pin: spdif-tx-pin { pins = "PB13"; function = "spdif"; bias-pull-up; }; /omit-if-no-ref/ spi0_pi_pins: spi0-pi-pins { pins = "PI11", "PI12", "PI13"; function = "spi0"; }; /omit-if-no-ref/ spi0_cs0_pi_pin: spi0-cs0-pi-pin { pins = "PI10"; function = "spi0"; }; /omit-if-no-ref/ spi0_cs1_pi_pin: spi0-cs1-pi-pin { pins = "PI14"; function = "spi0"; }; /omit-if-no-ref/ spi1_pi_pins: spi1-pi-pins { pins = "PI17", "PI18", "PI19"; function = "spi1"; }; /omit-if-no-ref/ spi1_cs0_pi_pin: spi1-cs0-pi-pin { pins = "PI16"; function = "spi1"; }; /omit-if-no-ref/ spi2_pb_pins: spi2-pb-pins { pins = "PB15", "PB16", "PB17"; function = "spi2"; }; /omit-if-no-ref/ spi2_cs0_pb_pin: spi2-cs0-pb-pin { pins = "PB14"; function = "spi2"; }; /omit-if-no-ref/ spi2_pc_pins: spi2-pc-pins { pins = "PC20", "PC21", "PC22"; function = "spi2"; }; /omit-if-no-ref/ spi2_cs0_pc_pin: spi2-cs0-pc-pin { pins = "PC19"; function = "spi2"; }; /omit-if-no-ref/ uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; }; /omit-if-no-ref/ uart0_pf_pins: uart0-pf-pins { pins = "PF2", "PF4"; function = "uart0"; }; /omit-if-no-ref/ uart1_pa_pins: uart1-pa-pins { pins = "PA10", "PA11"; function = "uart1"; }; /omit-if-no-ref/ uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins { pins = "PA12", "PA13"; function = "uart1"; }; /omit-if-no-ref/ uart2_pa_pins: uart2-pa-pins { pins = "PA2", "PA3"; function = "uart2"; }; /omit-if-no-ref/ uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins { pins = "PA0", "PA1"; function = "uart2"; }; /omit-if-no-ref/ uart2_pi_pins: uart2-pi-pins { pins = "PI18", "PI19"; function = "uart2"; }; /omit-if-no-ref/ uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins { pins = "PI16", "PI17"; function = "uart2"; }; /omit-if-no-ref/ uart3_pg_pins: uart3-pg-pins { pins = "PG6", "PG7"; function = "uart3"; }; /omit-if-no-ref/ uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { pins = "PG8", "PG9"; function = "uart3"; }; /omit-if-no-ref/ uart3_ph_pins: uart3-ph-pins { pins = "PH0", "PH1"; function = "uart3"; }; /omit-if-no-ref/ uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins { pins = "PH2", "PH3"; function = "uart3"; }; /omit-if-no-ref/ uart4_pg_pins: uart4-pg-pins { pins = "PG10", "PG11"; function = "uart4"; }; /omit-if-no-ref/ uart4_ph_pins: uart4-ph-pins { pins = "PH4", "PH5"; function = "uart4"; }; /omit-if-no-ref/ uart5_ph_pins: uart5-ph-pins { pins = "PH6", "PH7"; function = "uart5"; }; /omit-if-no-ref/ uart5_pi_pins: uart5-pi-pins { pins = "PI10", "PI11"; function = "uart5"; }; /omit-if-no-ref/ uart6_pa_pins: uart6-pa-pins { pins = "PA12", "PA13"; function = "uart6"; }; /omit-if-no-ref/ uart6_pi_pins: uart6-pi-pins { pins = "PI12", "PI13"; function = "uart6"; }; /omit-if-no-ref/ uart7_pa_pins: uart7-pa-pins { pins = "PA14", "PA15"; function = "uart7"; }; /omit-if-no-ref/ uart7_pi_pins: uart7-pi-pins { pins = "PI20", "PI21"; function = "uart7"; }; }; timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc24M>; }; wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc24M>; }; rtc: rtc@1c20d00 { compatible = "allwinner,sun7i-a20-rtc"; reg = <0x01c20d00 0x20>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; }; pwm: pwm@1c20e00 { compatible = "allwinner,sun7i-a20-pwm"; reg = <0x01c20e00 0xc>; clocks = <&osc24M>; #pwm-cells = <3>; status = "disabled"; }; spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-spdif"; reg = <0x01c21000 0x400>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; clock-names = "apb", "spdif"; dmas = <&dma SUN4I_DMA_NORMAL 2>, <&dma SUN4I_DMA_NORMAL 2>; dma-names = "rx", "tx"; status = "disabled"; }; ir0: ir@1c21800 { compatible = "allwinner,sun4i-a10-ir"; clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; clock-names = "apb", "ir"; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01c21800 0x40>; status = "disabled"; }; ir1: ir@1c21c00 { compatible = "allwinner,sun4i-a10-ir"; clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; clock-names = "apb", "ir"; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01c21c00 0x40>; status = "disabled"; }; i2s1: i2s@1c22000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22000 0x400>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 4>, <&dma SUN4I_DMA_NORMAL 4>; dma-names = "rx", "tx"; status = "disabled"; }; i2s0: i2s@1c22400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22400 0x400>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 3>, <&dma SUN4I_DMA_NORMAL 3>; dma-names = "rx", "tx"; status = "disabled"; }; lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun7i-a20-codec"; reg = <0x01c22c00 0x40>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; clock-names = "apb", "codec"; dmas = <&dma SUN4I_DMA_NORMAL 19>, <&dma SUN4I_DMA_NORMAL 19>; dma-names = "rx", "tx"; status = "disabled"; }; sid: eeprom@1c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; }; i2s2: i2s@1c24400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c24400 0x400>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 6>, <&dma SUN4I_DMA_NORMAL 6>; dma-names = "rx", "tx"; status = "disabled"; }; rtp: rtp@1c25000 { compatible = "allwinner,sun5i-a13-ts"; reg = <0x01c25000 0x100>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #thermal-sensor-cells = <0>; }; uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_APB1_UART0>; status = "disabled"; }; uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_APB1_UART1>; status = "disabled"; }; uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_APB1_UART2>; status = "disabled"; }; uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_APB1_UART3>; status = "disabled"; }; uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_APB1_UART4>; status = "disabled"; }; uart5: serial@1c29400 { compatible = "snps,dw-apb-uart"; reg = <0x01c29400 0x400>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_APB1_UART5>; status = "disabled"; }; uart6: serial@1c29800 { compatible = "snps,dw-apb-uart"; reg = <0x01c29800 0x400>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_APB1_UART6>; status = "disabled"; }; uart7: serial@1c29c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c29c00 0x400>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_APB1_UART7>; status = "disabled"; }; ps20: ps2@1c2a000 { compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a000 0x400>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB1_PS20>; status = "disabled"; }; ps21: ps2@1c2a400 { compatible = "allwinner,sun4i-a10-ps2"; reg = <0x01c2a400 0x400>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB1_PS21>; status = "disabled"; }; i2c0: i2c@1c2ac00 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB1_I2C0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@1c2b000 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB1_I2C1>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c2: i2c@1c2b400 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB1_I2C2>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c3: i2c@1c2b800 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b800 0x400>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB1_I2C3>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; can0: can@1c2bc00 { compatible = "allwinner,sun7i-a20-can", "allwinner,sun4i-a10-can"; reg = <0x01c2bc00 0x400>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB1_CAN>; status = "disabled"; }; i2c4: i2c@1c2c000 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2c000 0x400>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_APB1_I2C4>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; mali: gpu@1c40000 { compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; reg = <0x01c40000 0x10000>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1", "pmu"; clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; clock-names = "bus", "core"; resets = <&ccu RST_GPU>; assigned-clocks = <&ccu CLK_GPU>; assigned-clock-rates = <384000000>; }; gmac: ethernet@1c50000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x01c50000 0x10000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; clock-names = "stmmaceth", "allwinner_gmac_tx"; snps,pbl = <2>; snps,fixed-burst; snps,force_sf_dma_mode; status = "disabled"; gmac_mdio: mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; }; hstimer@1c60000 { compatible = "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_HSTIMER>; }; gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; #interrupt-cells = <3>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; fe0: display-frontend@1e00000 { compatible = "allwinner,sun7i-a20-display-frontend"; reg = <0x01e00000 0x20000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, <&ccu CLK_DRAM_DE_FE0>; clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_DE_FE0>; ports { #address-cells = <1>; #size-cells = <0>; fe0_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; fe0_out_be0: endpoint@0 { reg = <0>; remote-endpoint = <&be0_in_fe0>; }; fe0_out_be1: endpoint@1 { reg = <1>; remote-endpoint = <&be1_in_fe0>; }; }; }; }; fe1: display-frontend@1e20000 { compatible = "allwinner,sun7i-a20-display-frontend"; reg = <0x01e20000 0x20000>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, <&ccu CLK_DRAM_DE_FE1>; clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_DE_FE1>; ports { #address-cells = <1>; #size-cells = <0>; fe1_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; fe1_out_be0: endpoint@0 { reg = <0>; remote-endpoint = <&be0_in_fe1>; }; fe1_out_be1: endpoint@1 { reg = <1>; remote-endpoint = <&be1_in_fe1>; }; }; }; }; be1: display-backend@1e40000 { compatible = "allwinner,sun7i-a20-display-backend"; reg = <0x01e40000 0x10000>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, <&ccu CLK_DRAM_DE_BE1>; clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_DE_BE1>; ports { #address-cells = <1>; #size-cells = <0>; be1_in: port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; be1_in_fe0: endpoint@0 { reg = <0>; remote-endpoint = <&fe0_out_be1>; }; be1_in_fe1: endpoint@1 { reg = <1>; remote-endpoint = <&fe1_out_be1>; }; }; be1_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; be1_out_tcon0: endpoint@0 { reg = <0>; remote-endpoint = <&tcon0_in_be1>; }; be1_out_tcon1: endpoint@1 { reg = <1>; remote-endpoint = <&tcon1_in_be1>; }; }; }; }; be0: display-backend@1e60000 { compatible = "allwinner,sun7i-a20-display-backend"; reg = <0x01e60000 0x10000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, <&ccu CLK_DRAM_DE_BE0>; clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_DE_BE0>; ports { #address-cells = <1>; #size-cells = <0>; be0_in: port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; be0_in_fe0: endpoint@0 { reg = <0>; remote-endpoint = <&fe0_out_be0>; }; be0_in_fe1: endpoint@1 { reg = <1>; remote-endpoint = <&fe1_out_be0>; }; }; be0_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; be0_out_tcon0: endpoint@0 { reg = <0>; remote-endpoint = <&tcon0_in_be0>; }; be0_out_tcon1: endpoint@1 { reg = <1>; remote-endpoint = <&tcon1_in_be0>; }; }; }; }; }; };
/* * Copyright 2020 TCS - TurControlSysteme Ltd. * Milos Ladicorbic <[email protected]> * */ /dts-v1/; #include "sun7i-a20.dtsi" #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> / { model = "Tcs A20-tcs"; compatible = "tcs,a20-tcs", "allwinner,sun7i-a20"; aliases { serial0 = &uart0; serial1 = &uart6; serial2 = &uart7; spi0 = &spi1; spi1 = &spi2; }; chosen { stdout-path = "serial0:115200n8"; }; }; &ve { status = "okay"; }; &codec { status = "okay"; }; &cpu0 { cpu-supply = <®_dcdc2>; }; &de { status = "okay"; }; &ehci0 { status = "okay"; }; &ehci1 { status = "okay"; }; &gmac { pinctrl-names = "default"; pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>; phy-handle = <&phy1>; phy-mode = "mii"; status = "okay"; }; &i2c0 { status = "okay"; axp209: pmic@34 { reg = <0x34>; interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; }; }; &i2c1 { status = "okay"; }; &i2c2 { status = "okay"; }; &gmac_mdio { phy1: ethernet-phy@1 { reg = <1>; }; }; &mmc0 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 4 5 GPIO_ACTIVE_LOW>; /* PE5 */ status = "okay"; }; &ohci0 { status = "okay"; }; &ohci1 { status = "okay"; }; &otg_sram { status = "okay"; }; &pio { vcc-pa-supply = <®_vcc3v3>; vcc-pc-supply = <®_vcc3v3>; vcc-pe-supply = <®_ldo3>; vcc-pf-supply = <®_vcc3v3>; vcc-pg-supply = <®_ldo4>; gmac_txerr: gmac-txerr-pin { pins = "PA17"; function = "gmac"; }; }; #include "axp209.dtsi" &ac_power_supply { status = "okay"; }; ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1400000>; regulator-name = "vdd-cpu"; }; ®_dcdc3 { regulator-always-on; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1400000>; regulator-name = "vdd-int-dll"; }; ®_ldo2 { regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "avcc"; }; ®_ldo3 { regulator-always-on; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-name = "pe"; status = "okay"; }; ®_ldo4 { regulator-always-on; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-name = "pg"; status = "okay"; }; ®_usb0_vbus { status = "okay"; /* USB0-DRV PB9 */ }; ®_usb1_vbus { gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* USB1-DRV PB10 */ status = "okay"; }; ®_usb2_vbus { status = "okay"; }; &spi1 { pinctrl-names = "default"; pinctrl-0 = <&spi1_pi_pins>, <&spi1_cs0_pi_pin>; status = "okay"; }; &spi2 { pinctrl-names = "default"; pinctrl-0 = <&spi2_pc_pins>, <&spi2_cs0_pc_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; &uart6 { pinctrl-names = "default"; pinctrl-0 = <&uart6_pi_pins>; status = "okay"; }; &uart7 { pinctrl-names = "default"; pinctrl-0 = <&uart7_pi_pins>; status = "okay"; }; &usb_otg { dr_mode = "host"; status = "okay"; }; &usb_power_supply { status = "okay"; }; &usbphy { usb0_vbus-supply = <®_usb0_vbus>; /* USB0-DRV PB9 */ usb1_vbus-supply = <®_usb1_vbus>; /* USB1-DRV PH6 */ usb2_vbus-supply = <®_usb2_vbus>; /* USB2-DRV PH3 */ status = "okay"; };
/* * Copyright 2020 TCS - TurControlSysteme Ltd. * Milos Ladicorbic <[email protected]> * */ #include "sun7i-a20-tcs.dts" #include <dt-bindings/gpio/gpio.h> / { model = "sun7i-a20-tcs-7Zoll"; compatible = "tcs,a20-7Zoll", "allwinner,sun7i-a20"; mmc2_pwrseq: pwrseq { compatible = "mmc-pwrseq-emmc"; reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; }; backlight: backlight { /* LVDS Backlight Enable line */ compatible = "gpio-backlight"; power-supply = <®_lcdctrl5v0>; gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ }; reg_lcdctrl5v0: lcdctrl5v0 { compatible = "regulator-fixed"; regulator-name = "lcdctrl5v0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; enable-active-high; gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 - LCD_CTRL power pupply */ status = "okay"; }; lvds_panel: panel@1c16500 { compatible = "panel-lvds"; #address-cells = <1>; #size-cells = <0>; backlight = <&backlight>; power-supply = <®_lcdctrl5v0>; enable-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 STBY_DISPL */ reset-gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 RESET_DISPL */ status = "okay"; width-mm = <154>; height-mm = <85>; data-mapping = "vesa-24"; panel-timing { // 1024x600 @60Hz clock-frequency = <51000000>; hactive = <1024>; vactive = <600>; hsync-len = <1>; hfront-porch = <1>; hback-porch = <320>; vfront-porch = <1>; vback-porch = <35>; vsync-len = <1>; }; port { lvds_panel_input: endpoint { remote-endpoint = <&tcon0_out_lvds>; }; }; }; reg_cam: cam { compatible = "regulator-fixed"; regulator-name = "cam"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; vin-supply = <®_vcc5v0>; //gpio = <&pio 7 16 GPIO_ACTIVE_HIGH>; //enable-active-high; regulator-always-on; }; reg_cam_avdd: cam-avdd { compatible = "regulator-fixed"; regulator-name = "cam-avdd"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; status = "okay"; vin-supply = <®_cam>; }; reg_cam_dvdd: cam-dvdd { compatible = "regulator-fixed"; regulator-name = "cam-dvdd"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; status = "okay"; vin-supply = <®_cam>; }; reg_cam_dovdd: cam-dovdd { compatible = "regulator-fixed"; regulator-name = "cam-dovdd"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; status = "okay"; vin-supply = <®_cam>; }; }; &de { status = "okay"; }; ®_vcc5v0 { status = "okay"; }; &mmc2 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; mmc-pwrseq = <&mmc2_pwrseq>; status = "okay"; emmc: emmc@0 { reg = <0>; compatible = "mmc-card"; broken-hpi; }; }; &i2c2 { /* PB20 - PB21 */ status = "okay"; gt911: touchscreen@5d { compatible = "goodix,gt911"; reg = <0x5d>; interrupt-parent = <&pio>; interrupts = <7 12 IRQ_TYPE_EDGE_FALLING>; /* EINT12 (PH12) */ irq-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* INT (PH12) */ reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* RST (PH11) */ /*touchscreen-swapped-x-y;*/ }; }; &i2c1 { /* PB18 - PB19 */ status = "okay"; ov5640: camera@3c { compatible = "ovti,ov5640"; reg = <0x3c>; pinctrl-names = "default"; pinctrl-0 = <&csi1_clk_pg_pin>; clocks = <&ccu CLK_CSI1>; clock-names = "xclk"; clock-frequency = <24000000>; //reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; //powerdown-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH18 - STBY-EN */ reset-gpios = <&pio 7 14 GPIO_ACTIVE_LOW>; /* PH14 */ powerdown-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH15 */ AVDD-supply = <®_cam_avdd>; /* 2.8v */ DOVDD-supply = <®_cam_dovdd>; /* 2.8v */ DVDD-supply = <®_cam_dvdd>; /* 1.5v */ port { ov5640_to_csi: endpoint { remote-endpoint = <&csi_from_ov5640>; bus-width = <8>; data-shift = <2>; /* lines 9:2 are used */ hsync-active = <1>; /* Active high */ vsync-active = <0>; /* Active low */ data-active = <0>; /* Active high */ pclk-sample = <1>; /* Rising */ }; }; }; }; /* run CSI_1 8bit mode on PH port */ &csi1 { pinctrl-names = "default"; pinctrl-0 = <&csi1_8bits_ph_pins>; status = "okay"; port { #address-cells = <1>; #size-cells = <0>; csi_from_ov5640: endpoint { remote-endpoint = <&ov5640_to_csi>; bus-width = <8>; data-shift = <2>; /* lines 9:2 are used */ hsync-active = <1>; /* Active high */ vsync-active = <0>; /* Active low */ data-active = <0>; /* Active high */ pclk-sample = <1>; /* Rising */ }; }; }; /* connect tcon0_out_lvds -> lvds_panel_input */ &tcon0 { pinctrl-names = "default"; pinctrl-0 = <&lcd_lvds0_pins>; }; &tcon0_out { tcon0_out_lvds: endpoint@0 { reg = <0>; remote-endpoint = <&lvds_panel_input>; allwinner,tcon-channel = <0>; }; };
