Arm Cortex cores contain a Performance Monitoring Unit (PMU), that needs to be connected to the GIC distributor to be able to trigger interrupts. The actual interrupt IDs are an integration choice, so need to be advertised via the DT.
This series adds the DT nodes to the H3, H5 and H6 SoC .dtsi files. The interrupt IDs are not always as described in the manual (off by 4 for the A64 and H5), so the IRQs have been both tested in U-Boot and verified in Linux, using "perf record" (which requires working IRQs). Cheers, Andre. Andre Przywara (3): arm64: dts: allwinner: H6: Add PMU mode arm64: dts: allwinner: H5: Add PMU node arm: dts: allwinner: H3: Add PMU node arch/arm/boot/dts/sun8i-h3.dtsi | 15 ++++++++++++--- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 16 +++++++++++++--- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++ 3 files changed, 35 insertions(+), 6 deletions(-) -- 2.14.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20191121011835.8467-1-andre.przywara%40arm.com.
