On Fri, Aug 11, 2017 at 10:27 PM, Icenowy Zheng <[email protected]> wrote: > The pin controller of H5 has three IRQs at the chip's GIC, which > represents three banks of pinctrl IRQs. However, the device tree used to > miss the third IRQ of the pin controller, which makes the PG bank IRQ > not usable. > > Add the missing IRQ to the pinctrl node. > > Fixes: 4e36de179f27 ("arm64: allwinner: h5: add Allwinner H5 .dtsi") > Signed-off-by: Icenowy Zheng <[email protected]>
Applied as fixes for 4.13. ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
