Heh, that didn't go as I hoped,
I used gmane's interface hoping it would bump all the original lists and
users, since i don't have the original mail anymore I don't think :S
So sorry for the noise and l'll try to bump this more properly :)
On 08-08-15 20:45, Olliver Schinagl wrote:
Hey all,
Alexandru Gagniuc <mr.nuke.me@...> writes:
SPI transfers were limited to one FIFO depth, which is 64 bytes.
This was an artificial limitation, however, as the hardware can handle
much larger bursts. To accommodate this, we enable the interrupt when
the Rx FIFO is 3/4 full, and drain the FIFO within the interrupt
handler. The 3/4 ratio was chosen arbitrarily, with the intention to
reduce the potential number of interrupts.
Since the SUN4I_CTL_TP bit is set, the hardware will pause
transmission whenever the FIFO is full, so there is no risk of losing
data if we can't service the interrupt in time.
For the Tx side, enable and use the Tx FIFO 3/4 empty interrupt to
replenish the FIFO on large SPI bursts. This requires more care in
when the interrupt is left enabled, as this interrupt will continually
trigger when the FIFO is less than 1/4 full, even though we
acknowledge it.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@...>
Acked-by: Maxime Ripard <maxime.ripard@...>
This patch was posted more then a year ago and I think several tree's carry it.
I've used this patch in combination with the mmc-spi driver and found no
problems with it in the past year.
So have my Tested-by: Olliver Schinagl <[email protected]>
and lets get this patch merged!
P.S. I have the original patch and can resend it if needed.
<snip>
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