I was concerned that this would remove some barriers which were previously
implicitly present in the readl/writel calls.

Comparing the preprocessed code shows that the old code had compiler barrers
(not CPU instruction barriers) between the reads and writes while the new code
does everything as a single statement without barriers. I think this is safe.

In any case the generated code is identical (confirmed with objdump).

Signed-off-by: Ian Campbell <[email protected]>
---
 arch/arm/cpu/armv7/sunxi/pinmux.c | 21 +++------------------
 1 file changed, 3 insertions(+), 18 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c 
b/arch/arm/cpu/armv7/sunxi/pinmux.c
index 8f5cbfe..832545f 100644
--- a/arch/arm/cpu/armv7/sunxi/pinmux.c
+++ b/arch/arm/cpu/armv7/sunxi/pinmux.c
@@ -12,18 +12,13 @@
 
 int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
 {
-       u32 cfg;
        u32 bank = GPIO_BANK(pin);
        u32 index = GPIO_CFG_INDEX(pin);
        u32 offset = GPIO_CFG_OFFSET(pin);
        struct sunxi_gpio *pio =
            &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
 
-       cfg = readl(&pio->cfg[0] + index);
-       cfg &= ~(0xf << offset);
-       cfg |= val << offset;
-
-       writel(cfg, &pio->cfg[0] + index);
+       clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
 
        return 0;
 }
@@ -45,36 +40,26 @@ int sunxi_gpio_get_cfgpin(u32 pin)
 
 int sunxi_gpio_set_drv(u32 pin, u32 val)
 {
-       u32 drv;
        u32 bank = GPIO_BANK(pin);
        u32 index = GPIO_DRV_INDEX(pin);
        u32 offset = GPIO_DRV_OFFSET(pin);
        struct sunxi_gpio *pio =
            &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
 
-       drv = readl(&pio->drv[0] + index);
-       drv &= ~(0x3 << offset);
-       drv |= val << offset;
-
-       writel(drv, &pio->drv[0] + index);
+       clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val);
 
        return 0;
 }
 
 int sunxi_gpio_set_pull(u32 pin, u32 val)
 {
-       u32 pull;
        u32 bank = GPIO_BANK(pin);
        u32 index = GPIO_PULL_INDEX(pin);
        u32 offset = GPIO_PULL_OFFSET(pin);
        struct sunxi_gpio *pio =
            &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
 
-       pull = readl(&pio->pull[0] + index);
-       pull &= ~(0x3 << offset);
-       pull |= val << offset;
-
-       writel(pull, &pio->pull[0] + index);
+       clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, offset);
 
        return 0;
 }
-- 
1.9.0

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