On Sat, 15 Mar 2014, Carlo Caione wrote: > Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. > Three register are present to (un)mask, control and acknowledge NMI. > These two patches add a new irqchip driver in cascade with GIC.
If I get an ack for the DT parts, I'll pick it up. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
