I've been wanting to get SPI up and running on the cubie, which now is as simple as declaring the relevant nodes in devicetree. The issue here is how and where to declare the pingroups.
Take for example the fictional A1l sunli SoC: SPI0 on sunli has 5 signals, each muxable to one of two pins: signal | pin A | pin B ----------------------- CLK | PB0 | PF5 MOSI | PB1 | PF6 MISO | PB2 | PF6 CS0 | PB3 | PF8 CS1 | PB4 | PF0 One obvious solution would be to declare group_a and group_b. Simple. However, some boards may only use one of the CS signals. wens (sorry, I don't know your real name) suggested making a group for CLK,MOSI,MISO, one for CS0, and one for CS1. The peripheral would reference thegroup with CLK,MOSI,MISO, and one of the CS* groups. Considering our muxing options, that's a total of 6 declarations. And of course, this doesn't handle the case of boards doing funny things, such as using PF5, PB1, PB2, and PF8 for SPI. Such an arrangement is not impossible, and ight make sense depending on the arrangements of balls on the BGA package. One other solution would be to declare each pin (clk_a, clk_b, mosi_s, mosi_b, etc) as a group, but that would be a crapload of declarations. That's a ton of unneeded bloat IMHO. I think the best solution here is to just declare the pingroups in the board's dts, rather than the SoC's dtsi. Would this be acceptable for you guys? Alex -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
