On Thu, 2014-02-20 at 09:24 -0600, Rob Herring wrote:
> > +#define AHCI_PHYCS0R 0x00c0
> > +#define AHCI_PHYCS1R 0x00c4
> > +#define AHCI_PHYCS2R 0x00c8
[...]
> > +#define AHCI_RWCR 0x00fc
> These registers are not sunxi specific, but part of a certain vendor's
> IP found in several SOCs. I can't tell you who, but it shouldn't be
> too hard to figure out.
Actually, only the 4 above are used here and if I'm guessing which
certain vendor you mean correctly then the code for those has these in
its register map as reserved and doesn't touch them (this is true in
both of the similar drivers I looked at).
The rest of the registers in that list did look a lot the DW part
(judging from the existing u-boot drivers) though.
> > +#define BIT(x) (1<<x)
> > +static u32 sunxi_getbits(u8 *reg, u8 mask, u8 shift)
> > +{
> > + return (readl(reg) >> shift) & mask;
> > +}
> > +
> > +static int sunxi_ahci_phy_init(u32 base)
> > +{
> [...magic...]
> > +
>
> I would guess this code or something very similar already exists in u-boot.
I've had a look in the most obvious files in drivers/block/ and I don't
see anything. Perhaps I should look harder.
FWIW I also couldn't find anything similar in linux/drivers/ata.
Ian.
--
You received this message because you are subscribed to the Google Groups
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to [email protected].
For more options, visit https://groups.google.com/groups/opt_out.
