Manual/partial revert of 8690bbcf3b70 ("Introduce cpu_dcache_is_aliasing()
across all architectures")
Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
at least).
Legacy ARC700 cpus could be VIPT aliasing (based on cache geometry and
PAGE_SIZE) however recently that support was ripped out so VIPT aliasing
cache is not relevant to ARC anymore.
P.S. : This has been discussed a few times on lists [1]
P.S.2: Please CC the arch maintainers and/or mailing list before adding
such interfaces.
[1]
http://lists.infradead.org/pipermail/linux-snps-arc/2023-February/006899.html
Cc: Mathieu Desnoyers <mathieu.desnoy...@efficios.com>
Signed-off-by: Vineet Gupta <vgu...@kernel.org>
---
arch/arc/Kconfig | 1 -
arch/arc/include/asm/cachetype.h | 9 ---------
2 files changed, 10 deletions(-)
delete mode 100644 arch/arc/include/asm/cachetype.h
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 99d2845f3feb..4092bec198be 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -6,7 +6,6 @@
config ARC
def_bool y
select ARC_TIMERS
- select ARCH_HAS_CPU_CACHE_ALIASING
select ARCH_HAS_CACHE_LINE_SIZE
select ARCH_HAS_DEBUG_VM_PGTABLE
select ARCH_HAS_DMA_PREP_COHERENT
diff --git a/arch/arc/include/asm/cachetype.h b/arch/arc/include/asm/cachetype.h
deleted file mode 100644
index 05fc7ed59712..000000000000
--- a/arch/arc/include/asm/cachetype.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARC_CACHETYPE_H
-#define __ASM_ARC_CACHETYPE_H
-
-#include <linux/types.h>
-
-#define cpu_dcache_is_aliasing() true
-
-#endif
--
2.34.1
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