On Sun, 13 Aug 2023 12:25:43 -0700 Vineet Gupta <vgu...@kernel.org> wrote:
> Legacy ARC700 processors (first generation of MMU enabled ARC cores) has > VIPT cached which could be configured such that they could alias. > I added the VIPT aliasing support, with all the cache flush overhead to > support all but 1 silicon. That is long bygone and we can remove the > complexity and maintenance burden of that unneeded code. > > This also helps streamline support for new features such as generic folio > work. > This of course messes up Matthew's "arc: implement the new page table range API". Are you or Matthew up for redoing that patch? Alternatively, can you redo this patch on top of Matthew's patch (ie, against mm-unstable or linux-next)? Thanks. _______________________________________________ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
