On Mon, Mar 27, 2023 at 2:16 PM Arnd Bergmann <a...@kernel.org> wrote:
> From: Arnd Bergmann <a...@arndb.de> > > Most ARM CPUs can have write-back caches and that require > cache management to be done in the dma_sync_*_for_device() > operation. This is typically done in both writeback and > writethrough mode. > > The cache-v4.S (arm720/740/7tdmi/9tdmi) and cache-v4wt.S > (arm920t, arm940t) implementations are the exception here, > and only do the cache management after the DMA is complete, > in the dma_sync_*_for_cpu() operation. > > Change this for consistency with the other platforms. This > should have no user visible effect. > > Signed-off-by: Arnd Bergmann <a...@arndb.de> Looks good to me. Reviewed-by: Linus Walleij <linus.wall...@linaro.org> Yours, Linus Walleij _______________________________________________ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
