On Wed, Feb 15, 2023 at 08:59:18PM -0800, Vineet Gupta wrote:
> On 2/10/23 09:06, Matthew Wilcox wrote:
> > I see a discrepancy here ...
> >
> > arch/arc/include/asm/shmparam.h:
> > /* Handle upto 2 cache bins */
> > #define SHMLBA (2 * PAGE_SIZE)
> >
> > arch/arc/include/asm/cacheflush.h:
> > #define CACHE_COLORS_NUM 4
>
> The initial aliasing dcache support assumed 2 colors but was later bumped to
> 4, w/o making the adjustment in shmparam.h
OK. Will you fix it yourself, or do you want me to send a patch?
> > (there are some other problems with the arc cache flushing code;
>
> The VIPT aliasing config (which is pretty much dead and unused) or regular
> parts ?
I'm not sure. This is incorrect in flush_dcache_page():
} else if (page_mapcount(page)) {
[...]
unsigned long vaddr = page->index << PAGE_SHIFT;
If the page being flushed is a tail page, then page->index is not
valid, so you're essentially flushing a random address. I have a
fix for it that I sent out earlier this week.
> > I'm working on patches to address them, but those are things I understand a
> > little better. I know nothing about the ARC architecture itself)
>
> Legacy ARC700 cpus had VIPT D$. The cache size was configurable by Soc
> builder and the specific geometry could yield an aliasing configuration
> (e.g. standard page size 8K, 4 way set associative D$: so D$ > 32K were
> aliasing and needed CONFIG_ARC_CACHE_VIPT_ALIASING). Although there was ever
> only 1 customer who taped out an aliasing cache config.
>
> The newer ARC HS cores have PIPT D$ and thus don't need the aliasing
> support.
>
> FWIW we could rip out all the VIPT aliasing code as I don't think it is
> needed anymore. @Alexey can you confirm ?
>
> -Vineet
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