On 08/25/2016 04:49 AM, Alexey Brodkin wrote:
> ...
> [PERF_COUNT_ARC_EDTLB] = "edtlb", /* D-TLB Miss */
> [PERF_COUNT_ARC_EITLB] = "eitlb", /* I-TLB Miss */
> +
> + [PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc", /* Instr: mem read
> cached */
> + [PERF_COUNT_HW_CACHE_MISSES] = "dclm", /* D-cache Load Miss */
I think this is duplicating a mistake we already have. I vaguely remember when
doing some hackbench profiling last year with range based profiling confined to
memset routine and saw that L1-dcache-misses was counting zero. This is because
it
only counts LD misses while memset only does ST.
Performance counter stats for '/sbin/hackbench':
0 L1-dcache-misses
0 L1-dcache-load-misses
1846082 L1-dcache-store-misses
@PeterZ do you concur that is wrong and we ought to setup 2 counters to do this
correctly ?
-Vineet
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