From 926a68de91619f95399e4621d6b2d57bd0cf91e0 Mon Sep 17 00:00:00 2001 From: Yousong Zhou Date: Tue, 8 Sep 2015 14:24:58 +0800 Subject: [PATCH 1/2] mmc: sunxi: split setting mod_clk into 3 steps Signed-off-by: Yousong Zhou --- drivers/mmc/sunxi_mmc.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 25f18ad..e92b4a5 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -133,14 +133,24 @@ static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) sclk_dly = 4; } - writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) | - CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | - CCM_MMC_CTRL_M(div), mmchost->mclkreg); - debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n", mmchost->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div); + /* Disable mclk first */ + writel(0, mmchost->mclkreg); + udelay(500); + + writel(pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) | CCM_MMC_CTRL_N(n) | + CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | CCM_MMC_CTRL_M(div), + mmchost->mclkreg); + udelay(500); + + /* Re-enable mclk */ + writel(CCM_MMC_CTRL_ENABLE | readl(mmchost->mclkreg), + mmchost->mclkreg); + udelay(500); + return 0; } -- 1.7.10.4