Hi Geert

Thank you for your feedback

> >> Can't you loop over all MMC dividers, and
> >>   1. calculate the needed parent clock rate for that MMC divider,
> >>   2. use clk_set_rate_range()[*] to find a (close) parent clock rate,
> >>   3. calculate the effective clock rate based on MMC divider and parent
> >>      clock rate.
> >> and use the best effective clock rate found?
(snip)
> So the upper limit is a limitation of the MMCIF hardware, while the lower
> limit is a limitation of the CPG.
> 
> Then the upper limit should be either in the driver (as you did, using
> different compatible values), or it can be described in DT.
> (cfr. "git grep max.*freq -- arch/arm/boot/dts/").
> Personally, I'm leaning towards the latter.
> 
> IMHO the lower limit doesn't belong here.

I think I understood your opinion.
I will try this

Best regards
---
Kuninori Morimoto
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