Andrey Utkin <andrey.krieger.ut...@gmail.com> writes: > could you please point to some reading which explains this moment? Or > you just know this from experience? The solo device specs are very > terse about this, so I considered that it should work fine without > regard to how fast we write back to that register.
The SOLO IRQ controller does the common thing, all drivers (for chips using the relatively modern "write 1 to clear") have to follow this sequence: first ACK the interrupts sources (so they are deasserted, though they can be asserted again if new events arrive), and only then service the chip. > Also while you're at it, and if this really makes sense, you could > merge these two writes (unrecognized bits, then recognized bits) to > one write act. I think my patch does exactly this, merges both writes. -- Krzysztof Halasa Research Institute for Automation and Measurements PIAP Al. Jerozolimskie 202, 02-486 Warsaw, Poland -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
