On Sun, Jan 26, 2014 at 11:21:31AM +0000, Robert Longbottom wrote: > 0F0 000000F9 PLL_F_LO > 0F4 000000DC PLL_F_HI > 0F8 0000008E PLL_XCI
The PLL is enabled and configured for a 28.63636MHz input clock. With the default board config these registers are not touched at all, so this must be a remnant of testing with another board number. Please repeat with pll=35,35,35,35 . Daniel -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
