Devin, You've seen the clock stretch with your I2C analyzer?
Jean, How should clock stretches by slaves be handled using i2c-algo-bit? Regards, Andy Devin Heitmueller <dheitmuel...@kernellabs.com> wrote: >On Thu, Jan 13, 2011 at 8:21 AM, Jean Delvare <kh...@linux-fr.org> wrote: >> My bet is that register at 0x00 is a control register, and writing bit >> 7 (value 0x80) makes the chip busy enough that it can't process I2C >> requests at the same time. The following naks would be until the >> chip is operational again. > >Correct. Poking bit 7 of 0xE0:00 triggers the "send" for all the >bytes that were previously loaded into the device. It puts the chip >into a busy state, doing an i2c clock stretch until it is available >again. During that time it cannot see any i2c traffic, which is why >you are getting NAKs. > >Devin > >-- >Devin J. Heitmueller - Kernel Labs >http://www.kernellabs.com >-- >To unsubscribe from this list: send the line "unsubscribe linux-media" in >the body of a message to majord...@vger.kernel.org >More majordomo info at http://vger.kernel.org/majordomo-info.html N�����r��y����b�X��ǧv�^�){.n�+����{���bj)����w* jg��� �����ݢj/���z�ޖ��2�ޙ����&�)ߡ�a���� �G���h��j:+v���w��٥
