On i.MX8MQ/MM a separate control block contains registers for per-core
resets, clock gating, and fuse register control.

Signed-off-by: Philipp Zabel <p.za...@pengutronix.de>
---
 drivers/staging/media/hantro/hantro.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/staging/media/hantro/hantro.h 
b/drivers/staging/media/hantro/hantro.h
index 70a1cfee0281..4d037d1f0ac7 100644
--- a/drivers/staging/media/hantro/hantro.h
+++ b/drivers/staging/media/hantro/hantro.h
@@ -160,6 +160,7 @@ hantro_vdev_to_func(struct video_device *vdev)
  * @base:              Mapped address of VPU registers.
  * @enc_base:          Mapped address of VPU encoder register for convenience.
  * @dec_base:          Mapped address of VPU decoder register for convenience.
+ * @ctrl_base:         Mapped address of VPU control block.
  * @vpu_mutex:         Mutex to synchronize V4L2 calls.
  * @irqlock:           Spinlock to synchronize access to data structures
  *                     shared with interrupt handlers.
@@ -178,6 +179,7 @@ struct hantro_dev {
        void __iomem *base[HANTRO_MAX_REG_RANGES];
        void __iomem *enc_base;
        void __iomem *dec_base;
+       void __iomem *ctrl_base;
 
        struct mutex vpu_mutex; /* video_device lock */
        spinlock_t irqlock;
-- 
2.20.1

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