[PATCH] gpu: ipu-v3: Allow negative offsets for interlaced scanning

[Philipp Zabel]

The IPU also supports interlaced buffers that start with the bottom field.
To achieve this, the the base address EBA has to be increased by a stride
length and the interlace offset ILO has to be set to the negative stride.

Signed-off-by: Philipp Zabel <p.za...@pengutronix.de>
---
 drivers/gpu/ipu-v3/ipu-cpmem.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
index 9f2d9ec42add..c1028f38c553 100644
--- a/drivers/gpu/ipu-v3/ipu-cpmem.c
+++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
@@ -269,8 +269,14 @@ EXPORT_SYMBOL_GPL(ipu_cpmem_set_uv_offset);
 
 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride)
 {
+       u32 ilo;
+
        ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
-       ipu_ch_param_write_field(ch, IPU_FIELD_ILO, stride / 8);
+       if (stride >= 0)
+               ilo = stride / 8;
+       else
+               ilo = 0x100000 - (-stride / 8);
+       ipu_ch_param_write_field(ch, IPU_FIELD_ILO, ilo);
        ipu_ch_param_write_field(ch, IPU_FIELD_SLY, (stride * 2) - 1);
 };
 EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan);
-- 
2.17.1