Hello Maxime,

thank you for your feedback.

> > > +/*
> > > + * configure parallel port control lines polarity
> > > + *
> > > + * POLARITY CTRL0
> > > + * - [5]:PCLK polarity (0: active low, 1: active high)
> > > + * - [1]:HREF polarity (0: active low, 1: active high)
> > > + * - [0]:VSYNC polarity (mismatch here between
> > > + *datasheet and hardware, 0 is active high
> > > + *and 1 is active low...)
> >
> > I know that yourself and Maxime have both confirmed that VSYNC
> > polarity is inverted, but I am looking at HSYNC and VSYNC with a
> > logic analyser and I am dumping the values written to
> > OV5640_REG_POLARITY_CTRL00 and to me it looks like that HSYNC is
> > active HIGH when hsync_pol == 0, and VSYNC is active HIGH when
> > vsync_pol == 1.
>
> Which mode are you testing this on?

My testing environment is made of the sensor connected to a SoC with 8 data 
lines, vsync, hsync, and pclk, and of course I am specifying hsync-active, 
vsync-active, and pclk-sample in the device tree on both ends so that they 
configure themselves accordingly to work in DVP mode (V4L2_MBUS_PARALLEL), with 
the correct polarities.
Between the sensor and the SoC there is a noninverting bus transceiver (voltage 
translator), for my experiments I have plugged myself onto the outputs of this 
transceiver only to be compliant with the voltage level of my logic analyser.

>
> The non-active periods are insanely high in most modes (1896 for an
> active horizontal length of 640 in 640x480 for example), especially
> hsync, and it's really easy to invert the two.

I am looking at all the data lines, so that I don't confuse the non-active 
periods with the active periods, and with my setup what I reported is what I 
get. I wonder if this difference comes from the sensor revision at all? 
Unfortunately I can only test the one camera I have got.

Thanks,
Fab

>
> Maxime
>
> --
> Maxime Ripard, Bootlin (formerly Free Electrons)
> Embedded Linux and Kernel engineering
> http://bootlin.com



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