Manu Abraham wrote:

> For a lower sampling frequency (aka Symbol rate), you need a higher
> clock and or higher time period. For higher sampling rates (Symbol
> Rates) the the master clock has to be decimated to  avoid overflows

Sorry, an error in one part. ^^

For a lower SRATE, you need a lower clock and a longer period of
time. With a higher SRATE for the same coeffecients, you are bound
to overflow, unless you decimate certain register contents.
Recalculating those register values are quite tedious and lots of
calculations involved for a different master clock.

The result with a higher master clock (with the same coeffecients),
if you happened to see some positive results, it was the result of
some overflow or underflow, which is for sure.

Manu



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