--- alsa-driver-1.0.9b/alsa-kernel/pci/hda/hda_intel.c.orig	2005-05-30 15:33:44.000000000 -0400
+++ alsa-driver-1.0.9b/alsa-kernel/pci/hda/hda_intel.c	2005-08-24 11:11:31.970792648 -0400
@@ -70,6 +70,7 @@
 			 "{Intel, ICH7},"
 			 "{Intel, ESB2},"
 			 "{ATI, SB450},"
+			 "{ULi, M5461},"
 			 "{VIA, VT8251},"
 			 "{VIA, VT8237A}}");
 MODULE_DESCRIPTION("Intel HDA driver");
@@ -357,6 +358,8 @@
 	azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 	azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
 
+	/* set the corb size to 256 entries */
+	azx_writeb(chip, CORBSIZE, 0x02);
 	/* set the corb write pointer to 0 */
 	azx_writew(chip, CORBWP, 0);
 	/* reset the corb hw read pointer */
@@ -370,6 +373,8 @@
 	azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 	azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
 
+	/* set the rirb size to 256 entries */
+	azx_writeb(chip, RIRBSIZE, 0x02);
 	/* reset the rirb hw write pointer */
 	azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 	/* set N=1, get RIRB response interrupt for new entry */
@@ -1177,6 +1182,31 @@
 {
 	int i;
 
+	if (chip->pci->vendor == 0x10b9 && chip->pci->device == 0x5461)
+	{
+		int j;
+		for (j = 0; j < MAX_ICH6_DEV; j++) {
+			unsigned int off = sizeof(u32) * (j * AZX_MAX_FRAG * 4);
+			azx_dev_t *azx_dev = &chip->azx_dev[j];
+			azx_dev->bdl = (u32 *)(chip->bdl.area + off);
+			azx_dev->bdl_addr = chip->bdl.addr + off;
+			if (chip->position_fix == POS_FIX_POSBUF)
+				azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + j * 8);
+			if (j >= 4)
+				i = j+1;
+			else
+				i = j;
+			/* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
+			azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
+			/* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
+			azx_dev->sd_int_sta_mask = 1 << i;
+			/* stream tag: must be non-zero and unique */
+			azx_dev->index = i;
+			azx_dev->stream_tag = i + 1;
+		}
+	}
+	else
+	{	
 	/* initialize each stream (aka device)
 	 * assign the starting bdl address to each stream (device) and initialize
 	 */
@@ -1195,6 +1225,7 @@
 		azx_dev->index = i;
 		azx_dev->stream_tag = i + 1;
 	}
+	}
 
 	return 0;
 }
@@ -1297,6 +1328,15 @@
 	if ((err = pci_enable_device(pci)) < 0)
 		return err;
 
+{
+#if BITS_PER_LONG == 64
+#else
+u16 tmp3;
+pci_read_config_word(pci, 0x40, &tmp3);
+pci_write_config_word(pci, 0x40, tmp3 | 0x10);
+pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
+#endif
+}
 	chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
 	
 	if (NULL == chip) {
@@ -1458,6 +1498,7 @@
 	{ 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ESB2 */
 	{ 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ATI SB450 */
 	{ 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* VIA VT8251/VT8237A */
+	{ 0x10B9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ULi M5461 */
 	{ 0, }
 };
 MODULE_DEVICE_TABLE(pci, azx_ids);