Add documentation for bindings used by Exynos3250 devfreq driver.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/arm/samsung/exynos3250-devfreq.txt | 66 ++++++++++++++++++++++
1 file changed, 66 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/samsung/exynos3250-devfreq.txt
diff --git
a/Documentation/devicetree/bindings/arm/samsung/exynos3250-devfreq.txt
b/Documentation/devicetree/bindings/arm/samsung/exynos3250-devfreq.txt
new file mode 100644
index 000000000000..047955e9e371
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos3250-devfreq.txt
@@ -0,0 +1,66 @@
+Samsung Exynos3250 devfreq driver
+=================================
+
+The driver support changing frequencies and voltage for:
+ - memory controller and bus,
+ - peripheral buses (left and right).
+
+Memory controller and bus
+=========================
+Required properties:
+ - compatible : should be "samsung,exynos3250-busfreq-mif"
+ - reg : two sets (offset and length of the register) for PPMU registers
+ used by this devfreq driver
+ - clock-names : one clock of name "dmc" to manage frequency
+ - clocks : phandle and specifier for clock listed in clock-names property
+ - vdd_mif-supply : phandle to MIF voltage regulator
+
+Peripheral buses
+================
+Required properties:
+ - compatible : should be "samsung,exynos3250-busfreq-int"
+ - reg : two sets (offset and length of the register) for PPMU registers
+ used by this devfreq driver
+ - clock-names : names for PPMU clocks and bus clocks to manage frequencies;
+ All following clock names (and corresponding phandles) must be
+ provided:
+ - "ppmu_left", "ppmu_right",
+ - "aclk_400", "aclk_266", "aclk_200", "aclk_160", "aclk_gdl",
"aclk_gdr", "mfc";
+ - clocks : phandles and specifiers for clocks listed in clock-names property
+ - vdd_mif-supply : phandle to INT voltage regulator
+
+Example
+=======
+ busfreq_mif: busfreq@106A0000 {
+ compatible = "samsung,exynos3250-busfreq-mif";
+ reg = <0x106A0000 0x2000>, <0x106B0000 0x2000>;
+ clocks = <&cmu_dmc CLK_DIV_DMC>;
+ clock-names = "dmc";
+ vdd_mif-supply = <&buck1_reg>;
+ status = "okay";
+ };
+
+ busfreq_int: busfreq@116A0000 {
+ compatible = "samsung,exynos3250-busfreq-int";
+ reg = <0x116A0000 0x2000>, <0x112A0000 0x2000>;
+ clocks = <&cmu CLK_PPMULEFT>,
+ <&cmu CLK_PPMURIGHT>,
+ <&cmu CLK_DIV_ACLK_400_MCUISP>,
+ <&cmu CLK_DIV_ACLK_266>,
+ <&cmu CLK_DIV_ACLK_200>,
+ <&cmu CLK_DIV_ACLK_160>,
+ <&cmu CLK_DIV_GDL>,
+ <&cmu CLK_DIV_GDR>,
+ <&cmu CLK_DIV_MFC>;
+ clock-names = "ppmuleft",
+ "ppmuright",
+ "aclk_400",
+ "aclk_266",
+ "aclk_200",
+ "aclk_160",
+ "aclk_gdl",
+ "aclk_gdr",
+ "mfc";
+ vdd_int-supply = <&buck3_reg>;
+ status = "okay";
+ };
--
1.9.1
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