Hi, On Thu, Aug 7, 2014 at 5:57 AM, Heiko Stübner <[email protected]> wrote: > PLLs on Rockchip platforms report their locking state in an external > register situated in the "General Register Files" which is provided > through a syscon device. > > When the initial clk init runs, this syscon is of course not yet > available, making it impossible to set PLLs to other frequencies > through the assigned-rate property of the clock-controller node. > > Syscon devices are initialized through a postcore initcall, so add an > arch_initcall to rerun the rockchip specific clock initalization when > the GRF is available. > > As the clock init already runs two times (through of_clk_add_provider > and of_clk_init), a third time shouldn't hurt to much and in the best > case wouldn't change any settings at all. > > Signed-off-by: Heiko Stuebner <[email protected]> > --- > drivers/clk/rockchip/clk.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+)
My current understanding is that this patch is on hold pending <https://patchwork.kernel.org/patch/4945531/> (AKA mfd: syscon: Decouple syscon interface from platform devices). If that patch lands then we can drop this one. -Doug -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
