On 11/03/2013 04:02 AM, Andreas Werner wrote:
> Revision 2:
> added comment in code.
>
> This patch adds the Write-through memory type in combination with mtrr.
> If you call ioremap_cache to request cachable memory (write-back) the
> function tries to set the PAT to write-back only if the mtrr setting of
> the requested region is also marked as Write-Back.
>
> If the mttr regions are marked e.g. as Write-through or with other
> types, the function will always return UC- memory.
>
> If you check the Intel document " IA-32 SDM vol 3a table Effective
> Memory Type", there
> are many other combinations possible.
>
> This patch will only add the following combination:
> PAT=Write-Back + MTRR=Write-Through.
>
> Since marking IO Memory as cachable is not valid, WT is the
> best way for caching/bursting on MMIO Devices.
>
> Tested on - Intel (R) Atom E680 (Tunnel Creek)
> - Intel (R) Core(TM)2 Duo
>
> Signed-off-by: Andreas Werner <[email protected]>
I don't quite know where this ended up, but I am *really* not happy
about going back to using MTRRs to mark I/O devices with the chronic
problems of MTRR exhaustion that entails. As such I do insist that PAT
is properly updated to support WT if we're going to do this.
-hpa
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