Hi,
I have been working on a small patch to add support for AMD756 PCI IRQ
Routing with linux-2.4.5
This has been tested with a Gigabyte 7IXE 7F board and several PCI cards,
including a SMC-Lucent PCI Cardbus Bridge which doesn't get an IRQ
assigned by the BIOS.
If anybody has a board based on this chipset I would appreciate further
testing and advise about the patch.
In this alpha version, I left two printk() lines to get information
about the IRQ settings.
You should get an output like the following:
[root@klingon ~]# dmesg | grep 756
PCI: Using IRQ router AMD756 VIPER [1022/740b] at 00:07.3
AMD756: dev 104c:ac1c, router pirq : 4 get irq : 0
AMD756: dev 104c:ac1c, router pirq : 4 get irq : 0
AMD756: dev 10ec:8029, router pirq : 3 get irq : 10
AMD756: dev 104c:ac1c, router pirq : 4 get irq : 0
AMD756: dev 104c:ac1c, router pirq : 4 SET irq : 5
AMD756: dev 104c:ac1c, router pirq : 4 get irq : 5
AMD756: dev 11fe:0005, router pirq : 1 get irq : 12
Thanks.
diff -u linux-2.4.5/arch/i386/kernel/pci-irq.c \
linux/arch/i386/kernel/pci-irq.c > linux-2.4.5_amd756-pci-routing-alpha1.patch
--
Jhon H. Caicedo O. <[EMAIL PROTECTED]>
Observatorio Sismol�gico del SurOccidente O.S.S.O
http://www.osso.org.co
Cali - Colombia
--- linux-2.4.5/arch/i386/kernel/pci-irq.c Wed May 16 12:25:39 2001
+++ linux/arch/i386/kernel/pci-irq.c Tue Jun 19 13:20:47 2001
@@ -391,6 +391,56 @@
return 1;
}
+/*
+ * Jun/19/2001 Support for AMD756 PCI Router (Alpha Release)
+ * Jhon H. Caicedo <[EMAIL PROTECTED]>
+ * The AMD756 pirq rules are nibble-based
+ * offset 0x56 0-3 PIRQA 4-7 PIRQB
+ * offset 0x57 0-3 PIRQC 4-7 PIRQD
+ */
+static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
+{
+ u8 irq_value;
+ u8 irq;
+
+ if (pirq < 5)
+ {
+ if (pirq < 3)
+ pci_read_config_byte(router, 0x56, &irq_value);
+ else
+ pci_read_config_byte(router, 0x57, &irq_value);
+ if (pirq & 1)
+ irq = irq_value & 15;
+ else
+ irq = irq_value >> 4;
+ printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq :
+%2d\n",
+ dev->vendor, dev->device, pirq, irq);
+ return irq;
+ }
+ return 0;
+}
+
+static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int
+irq)
+{
+ u8 irq_value;
+ u8 offset;
+
+ printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
+ dev->vendor, dev->device, pirq, irq);
+
+ if (pirq < 3)
+ offset = 0x56;
+ else
+ offset = 0x57;
+ pci_read_config_byte(router, offset, &irq_value);
+ if (pirq & 1)
+ irq_value = (irq_value & 0xF0) | irq;
+ else
+ irq_value = (irq_value & 0x0F) | (irq << 4);
+ pci_write_config_byte(router, offset, irq_value);
+ return 1;
+}
+
#ifdef CONFIG_PCI_BIOS
static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int
irq)
@@ -426,6 +476,8 @@
{ "VLSI 82C534", PCI_VENDOR_ID_VLSI, PCI_DEVICE_ID_VLSI_82C534, pirq_vlsi_get,
pirq_vlsi_set },
{ "ServerWorks", PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4,
pirq_serverworks_get, pirq_serverworks_set },
+ { "AMD756 VIPER", PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B,
+ pirq_amd756_get, pirq_amd756_set },
{ "default", 0, 0, NULL, NULL }
};
