>>> On 21.08.13 at 19:28, Andy Lutomirski <[email protected]> wrote: > On Wed, Aug 21, 2013 at 6:48 AM, David Vrabel <[email protected]> wrote: >> All, >> >> 179ef71c (mm: save soft-dirty bits on swapped pages) introduces a new >> PTE bit on x86 _PTE_SWP_SOFT_DIRTY which has the same value as _PTE_PSE >> and _PTE_PAT. >> >> With a Xen PV guest, the use of the _PTE_PAT will result in the page >> having unexpected cachability which will introduce a range of subtle >> performance and correctness issues. Xen programs the entry 4 in the PAT >> table with WC so a page that was previously WB will end up as WC. >> > > Kind of off topic, but do you have a summary of how Xen uses the high > PAT bits? I'm the one who wants WT, and if there's already precedent > for using the high PAT bits, it'll be helpful.
Xen's public headers have a comment explaining this, with the main information being this table: * The PAT MSR is as follow (it is a 64-bit value, each entry is 8 bits): * PAT4 PAT0 * +---+----+----+----+-----+----+----+ * WC | WC | WB | UC | UC- | WC | WB | <= Linux * +---+----+----+----+-----+----+----+ * WC | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) * +---+----+----+----+-----+----+----+ * WC | WP | WC | UC | UC- | WT | WB | <= Xen * +---+----+----+----+-----+----+----+ i.e. Xen is retaining the BIOS (and legacy from non-PAT times) meaning of the low four entries, putting WC and WP up into the high half. The fact that the entry 6 is defined to be WC is perhaps a mistake - it should really be considered reserved for an eventual future memory type (just like entry 7). It also seems like entry 6 is documented incorrectly here for Linux and BIOS. Jan -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
