This series builds on Andrew Jones's earlier RFC [1]. It lets userspace check for RVA23U64 conformance in one call, instead of walking hwprobe + prctl across every mandatory extension.
The series adds a small framework that resolves profile-class bases (IMA and RVA23U64) from the kernel's ISA extension bitmap at init time, and surfaces the result through both /proc/cpuinfo and hwprobe. Later patches can add RVA23S64, and backward RVA22 / RVA20 detection, to riscv_set_isa_bases() without changes to the surrounding code. Note: starting with v6, this series is sent from my Qualcomm address, [email protected]. Earlier versions came from my personal [email protected] (v3-v5). Patches 1-6 of v5 have been applied by Paul Walmsley (1-3 through riscv/fixes for v7.2-rc, 4-6 queued in riscv/for-next for v7.3), so v6 carries the remaining 11 patches, rebased onto riscv/for-next. Series outline (v6): Per-extension cpufeature parsing + hwprobe export: 1. B (the Zba/Zbb/Zbs set). Zic64b (new first-class extension): 2. dt-bindings: require a cbom/cbop/cboz block-size property whenever the matching Zicbom/Zicbop/Zicboz is present. 3. Zic64b dt-binding, with a schema check. 4. Zic64b cpufeature parsing + hwprobe export. 5-7. dts: declare zic64b in the SpacemiT K3, SpacemiT K1, and Sophgo SG2044 device trees. RVA23U64 base detection and exposure: 8. riscv_have_user_pmlen(): accessor for user pointer-masking PMLEN support. 9. cpufeature: per-hart and host-wide isa_bases bitmaps; IMA and RVA23U64 detection lives here. 10. /proc/cpuinfo: print "isa bases:" and "hart isa bases:", e.g. rva23u64. 11. hwprobe: expose RVA23U64. A follow-up series exposing these extensions to KVM guests (extending the KVM ISA extension ONE_REG interface) will be prepared on top of this one and will be posted separately. Tested on QEMU: with -cpu rva23s64,sv39=on, /proc/cpuinfo reports "isa bases : rv64ima rva23u64" on both the aggregated and per-hart lines, and hwprobe RISCV_HWPROBE_KEY_BASE_BEHAVIOR returns BASE_BEHAVIOR_IMA | BASE_BEHAVIOR_RVA23U64. A branch is available for all patches in the series: [2]. Link: https://lore.kernel.org/linux-riscv/[email protected]/ [1] Link: https://github.com/docularxu/linux/commits/b4/rva23u64-hwprobe-v6/ [2] Changes in v6: - Rebased onto riscv/for-next; dropped patches 1-6 of v5, which have been applied by Paul. - dt-bindings block-size: only match nodes that have riscv,isa-extensions (fix suggested by Conor, breakage reported by Rob's bot). - Zic64b dt-binding: guard the zic64b rule the same way (same defect class, found while fixing the above). - Follow the _BITULL() style of commit 8da45c93dfa9 ("RISC-V: hwprobe: Use BIT macro to avoid warnings") for the new hwprobe bits (EXT_B, EXT_ZIC64B, BASE_BEHAVIOR_RVA23U64). - Zic64b: RISCV_ISA_EXT_ZIC64B renumbered 110 to 116 after upstream additions took 106-111. - Link to v5: https://patch.msgid.link/[email protected] Changes in v5: - Rebased onto v7.2-rc1. - New patch: make riscv,cbom/cbop/cboz-block-size required whenever the matching Zicbom/Zicbop/Zicboz extension is present (Conor). - Ziccamoa/Za64rs: drop the Zaamo/Zalrsc validate callbacks (Conor). - Zic64b dt-binding: fix a double space in the commit message (Conor). - Collected Reviewed-by and Acked-by tags in v4. - Link to v4: https://patch.msgid.link/[email protected] Changes in v4: - New patch: sort the multi-letter Z extensions alphanumerically in the dt-binding (Conor), and place zic64b at its sorted position. - Zic64b cpufeature: validate only the CBO block sizes that are present; overlaps Qingwei Hu's earlier patch, so it is now authored by Qingwei. - Document EXT_ZICFISS / EXT_ZICFILP: cite the riscv-cfi v1.0 tag commit. - Picked up Inochi Amaoto's Acked-by (SG2044 dts) and Andrew Jones's Reviewed-by (documentation patch). - Link to v3: https://patch.msgid.link/[email protected] Changes in v3: - Add Zic64b as a first-class ISA extension: dt-binding, cpufeature parsing with a validate check, hwprobe export, and device-tree declarations for K3/K1/SG2044. - Patch 1 is now a clean up of hwprobe.rst indentation. - Document RISCV_HWPROBE_EXT_ZICFILP alongside ZICFISS. - Move the Zicclsm hwprobe.rst entry to the IMA_EXT_1 section to match its bit allocation. - Collect Anup Patel's Acked-by/Reviewed-by on Patch 3, the capitalization. - In cpufeature.c, set the local ext_mask with __set_bit(). - Update Guodong Xu's email to [email protected]. - Link to v2: https://patch.msgid.link/[email protected] Changes in v2 (since Andrew's RFC v1): - Rebased onto v7.1-rc2. - Reworked rva23u64 detection into per-hart and host isa_bases bitmaps, shared by /proc/cpuinfo and hwprobe. - Scoped to IMA and RVA23U64 (RVA23S64, RVA20/RVA22 cpuinfo output deferred). - Link to v1: https://lore.kernel.org/linux-riscv/[email protected] Signed-off-by: Guodong Xu <[email protected]> --- Andrew Jones (2): riscv: Add B to hwcap and hwprobe riscv: Add a getter for user PMLEN support Guodong Xu (8): dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz dt-bindings: riscv: Add Zic64b extension description riscv: dts: spacemit: k3: Add Zic64b ISA extension riscv: dts: spacemit: k1: Add Zic64b ISA extension riscv: dts: sophgo: sg2044: Add Zic64b ISA extension riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection riscv: cpu: Output isa bases lines in cpuinfo riscv: hwprobe: Introduce rva23u64 base behavior Qingwei Hu (1): riscv: Add Zic64b to cpufeature and hwprobe Documentation/arch/riscv/hwprobe.rst | 16 +++ .../devicetree/bindings/riscv/extensions.yaml | 54 +++++++++ arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 128 ++++++++++----------- arch/riscv/boot/dts/spacemit/k1.dtsi | 80 ++++++------- arch/riscv/boot/dts/spacemit/k3.dtsi | 48 ++++---- arch/riscv/include/asm/cpufeature.h | 14 +++ arch/riscv/include/asm/hwcap.h | 2 + arch/riscv/include/asm/processor.h | 4 + arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/hwprobe.h | 5 +- arch/riscv/kernel/cpu.c | 26 +++++ arch/riscv/kernel/cpufeature.c | 117 +++++++++++++++++++ arch/riscv/kernel/process.c | 12 ++ arch/riscv/kernel/sys_hwprobe.c | 25 ++-- tools/testing/selftests/riscv/hwprobe/which-cpus.c | 2 +- 15 files changed, 397 insertions(+), 137 deletions(-) --- base-commit: acf3fcb5e9199cc96ca033ec3c7570b6564c2e9e change-id: 20260508-rva23u64-hwprobe-v2-1d20739cbb8e Best regards, -- Guodong Xu <[email protected]>
