From: Anuj Gupta <[email protected]> Add SGL support in addition to PRP for dmabuf-backed requests, coalescing the mapping's sg_table into NVMe SGL data descriptors.
Signed-off-by: Anuj Gupta <[email protected]> [pavel: rebased] Signed-off-by: Pavel Begunkov <[email protected]> --- drivers/nvme/host/pci.c | 191 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 187 insertions(+), 4 deletions(-) diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index f1b67c191892..cbb321fb7c50 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -1287,12 +1287,18 @@ static blk_status_t nvme_pci_setup_data_prp(struct request *req, return BLK_STS_IOERR; } +static void nvme_pci_sgl_set_data_addr(struct nvme_sgl_desc *sge, + dma_addr_t addr, u32 len) +{ + sge->addr = cpu_to_le64(addr); + sge->length = cpu_to_le32(len); + sge->type = NVME_SGL_FMT_DATA_DESC << 4; +} + static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, struct blk_dma_iter *iter) { - sge->addr = cpu_to_le64(iter->addr); - sge->length = cpu_to_le32(iter->len); - sge->type = NVME_SGL_FMT_DATA_DESC << 4; + nvme_pci_sgl_set_data_addr(sge, iter->addr, iter->len); } static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, @@ -1303,6 +1309,158 @@ static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; } +static unsigned int nvme_pci_dmabuf_sgl_nents(struct request *req, + dma_addr_t *first_dma, + u32 *first_len) +{ + struct bio *bio = req->bio; + struct nvme_dmabuf_map *map = to_nvme_dmabuf_map(bio->bi_dmabuf_map); + struct scatterlist *sg; + unsigned long tmp; + size_t offset = bio->bi_iter.bi_offset; + size_t remaining = blk_rq_payload_bytes(req); + dma_addr_t last_end = 0; + unsigned int nents = 0; + dma_addr_t dma = 0; + u32 len = 0; + bool have = false; + + for_each_sgtable_dma_sg(map->sgt, sg, tmp) { + size_t sg_len = sg_dma_len(sg); + dma_addr_t addr = sg_dma_address(sg); + + if (!remaining) + break; + if (offset >= sg_len) { + offset -= sg_len; + continue; + } + + addr += offset; + sg_len -= offset; + offset = 0; + + while (sg_len && remaining) { + u32 chunk = min_t(size_t, remaining, sg_len); + + if (!have || last_end != addr) { + nents++; + if (nents == 1) { + dma = addr; + len = chunk; + } + } else if (nents == 1) { + len += chunk; + } + + have = true; + last_end = addr + chunk; + addr += chunk; + sg_len -= chunk; + remaining -= chunk; + } + } + + if (unlikely(remaining)) + return 0; + + *first_dma = dma; + *first_len = len; + return nents; +} + +static blk_status_t nvme_rq_setup_dmabuf_sgl(struct request *req, + struct nvme_queue *nvmeq, + unsigned int entries, + dma_addr_t first_dma, u32 first_len) +{ + struct nvme_iod *iod = blk_mq_rq_to_pdu(req); + struct bio *bio = req->bio; + struct nvme_dmabuf_map *map = to_nvme_dmabuf_map(bio->bi_dmabuf_map); + size_t length = blk_rq_payload_bytes(req); + struct nvme_sgl_desc *sg_list = NULL; + dma_addr_t sgl_dma = 0, last_end = 0; + unsigned int mapped = 0; + unsigned long tmp; + struct scatterlist *sg; + size_t offset, remaining; + bool have = false; + + if (!entries) + return BLK_STS_IOERR; + if (entries > NVME_MAX_SEGS) + return BLK_STS_AGAIN; + + iod->cmd.common.flags = NVME_CMD_SGL_METABUF; + iod->total_len = length; + + nvme_dmabuf_map_sync_for_device(nvmeq->dev, req); + + if (entries == 1) { + nvme_pci_sgl_set_data_addr(&iod->cmd.common.dptr.sgl, first_dma, + first_len); + return BLK_STS_OK; + } + + if (entries <= NVME_SMALL_POOL_SIZE / sizeof(*sg_list)) + iod->flags |= IOD_SMALL_DESCRIPTOR; + + sg_list = dma_pool_alloc(nvme_dma_pool(nvmeq, iod), GFP_ATOMIC, + &sgl_dma); + if (!sg_list) + return BLK_STS_RESOURCE; + iod->descriptors[iod->nr_descriptors++] = sg_list; + + offset = bio->bi_iter.bi_offset; + remaining = length; + + for_each_sgtable_dma_sg(map->sgt, sg, tmp) { + size_t sg_len = sg_dma_len(sg); + dma_addr_t addr = sg_dma_address(sg); + + if (!remaining) + break; + if (offset >= sg_len) { + offset -= sg_len; + continue; + } + + addr += offset; + sg_len -= offset; + offset = 0; + + while (sg_len && remaining) { + u32 chunk = min_t(size_t, remaining, sg_len); + + if (have && last_end == addr) { + u32 old = le32_to_cpu(sg_list[mapped - 1].length); + + sg_list[mapped - 1].length = cpu_to_le32(old + chunk); + } else { + if (WARN_ON_ONCE(mapped == entries)) + goto err_free; + nvme_pci_sgl_set_data_addr(&sg_list[mapped++], + addr, chunk); + } + have = true; + last_end = addr + chunk; + addr += chunk; + sg_len -= chunk; + remaining -= chunk; + } + } + + if (unlikely(remaining)) + goto err_free; + + nvme_pci_sgl_set_seg(&iod->cmd.common.dptr.sgl, sgl_dma, mapped); + return BLK_STS_OK; +err_free: + iod->nr_descriptors--; + dma_pool_free(nvme_dma_pool(nvmeq, iod), sg_list, sgl_dma); + return BLK_STS_IOERR; +} + static blk_status_t nvme_pci_setup_data_sgl(struct request *req, struct blk_dma_iter *iter) { @@ -1397,8 +1555,33 @@ static blk_status_t nvme_map_data(struct request *req) struct blk_dma_iter iter; blk_status_t ret; - if (blk_mq_rq_is_dmabuf(req)) + if (blk_mq_rq_is_dmabuf(req)) { + if (use_sgl != SGL_UNSUPPORTED) { + dma_addr_t first_dma; + u32 first_len; + unsigned int entries; + + entries = nvme_pci_dmabuf_sgl_nents(req, &first_dma, + &first_len); + + if (use_sgl == SGL_FORCED) { + ret = nvme_rq_setup_dmabuf_sgl(req, nvmeq, + entries, first_dma, first_len); + return ret == BLK_STS_AGAIN ? BLK_STS_IOERR : ret; + } + + if (sgl_threshold && entries && + DIV_ROUND_UP(blk_rq_payload_bytes(req), entries) >= + sgl_threshold) { + ret = nvme_rq_setup_dmabuf_sgl(req, nvmeq, + entries, first_dma, first_len); + if (ret != BLK_STS_AGAIN) + return ret; + } + } + return nvme_rq_setup_dmabuf_map(req, nvmeq); + } /* * Try to skip the DMA iterator for single segment requests, as that -- 2.54.0
