This series adds support for the PCIe0 PHY found in the SM8475 SoC. The initialization sequence varies noticeably when compared to the one used in the SM8450 SoC, hence the need to add support for this PHY.
Signed-off-by: Esteban Urrutia <[email protected]> --- Changes in v2: - Split series in subseries (pcie, usbss) - Sorry, it should have been like this from the start! - Link to v1: https://patch.msgid.link/[email protected] --- Esteban Urrutia (3): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SM8475 QMP PHY phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets phy: qcom: qmp-pcie: Add support for SM8475 Gen3x1 PCIe0 port .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 + drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 109 +++++++++++++++++++++ 2 files changed, 111 insertions(+) --- base-commit: cc2b5f627e8ccbae1188ef2d8be3e451d7f933a5 change-id: 20260714-sm8475-bup-pcie-3e3796e61c4e Best regards, -- Esteban Urrutia <[email protected]>
