This series adds support for both the PCIe0 and the QMP USB PHYs which can be found on the SM8475 SoC. The initialization sequences vary noticeably when compared to the ones used in the SM8450 SoC, hence the need to add support for these PHYs.
Signed-off-by: Esteban Urrutia <[email protected]> --- Esteban Urrutia (6): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SM8475 QMP PHY phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets phy: qcom: qmp-pcie: Add support for SM8475 Gen3x1 PCIe0 port dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8475 QMP PHY phy: qcom: qmp-combo: Add serdes and RBR/HBR/HBR2/HBR3 tables for v1 DP PLLs phy: qcom: qmp-combo: Add SM8475 support .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 + .../phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 1 + drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 259 +++++++++++++++++---- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 109 +++++++++ 4 files changed, 326 insertions(+), 45 deletions(-) --- base-commit: 49362394dad7df66c274c867a271394c10ca2bb8 change-id: 20260714-sm8475-bup-5c80d5f0b2ba Best regards, -- Esteban Urrutia <[email protected]>
