On Mon, May 11, 2026 at 09:34:49PM -0400, Guodong Xu wrote: > From: Jesse Taube <[email protected]> > > Zicclsm requires misaligned support for all regular load and store > instructions, both scalar and vector, but not AMOs or other > specialized forms of memory access, to main memory regions with both > the cacheability and coherence PMAs, as defined in the profiles spec. > Even though mandated, misaligned loads and stores might execute > extremely slowly. Standard software distributions should assume their > existence only for correctness, not for performance. > > Reviewed-by: Conor Dooley <[email protected]> > Reviewed-by: Andy Chiu <[email protected]> > Reviewed-by: Charlie Jenkins <[email protected]> > Tested-by: Charlie Jenkins <[email protected]> > Signed-off-by: Jesse Taube <[email protected]> > [Rebased, rewrote doc text, minor commit message revisions] > Signed-off-by: Andrew Jones <[email protected]> > Signed-off-by: Guodong Xu <[email protected]> > > --- > v2: > - Rebased onto v7.1-rc2; moved ZICCLSM to IMA_EXT_1 and > allocated a new bit for it > --- > Documentation/arch/riscv/hwprobe.rst | 4 ++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/uapi/asm/hwprobe.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > arch/riscv/kernel/sys_hwprobe.c | 1 + > 5 files changed, 8 insertions(+) > > diff --git a/Documentation/arch/riscv/hwprobe.rst > b/Documentation/arch/riscv/hwprobe.rst > index c3bb26d70c748..05f746061f679 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -289,6 +289,10 @@ The following keys are defined: > defined in the RISC-V ISA manual starting from commit f88abf1 > ("Integrating > load/store pair for RV32 with the main manual") of the > riscv-isa-manual. > > + * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension is supported, > + as defined in the RISC-V Profiles specification starting from commit > + b1d80660 ("Updated to ratified state.")
Sashiko[1] points out that now that this has been moved to IMA_EXT_1 it is no longer the correct location. [1] https://sashiko.dev/#/patchset/20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc%40riscstar.com Thanks, drew > + > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar > values to > :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was > mistakenly classified as a bitmask rather than a value. > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 44bf8c7d8acc5..e8f4a7dd96a93 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -112,6 +112,7 @@ > #define RISCV_ISA_EXT_ZCLSD 103 > #define RISCV_ISA_EXT_ZICFILP 104 > #define RISCV_ISA_EXT_ZICFISS 105 > +#define RISCV_ISA_EXT_ZICCLSM 106 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h > b/arch/riscv/include/uapi/asm/hwprobe.h > index 9139edba0aecb..6819df159c51e 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -116,6 +116,7 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE 15 > #define RISCV_HWPROBE_KEY_IMA_EXT_1 16 > #define RISCV_HWPROBE_EXT_ZICFISS (1ULL << 0) > +#define RISCV_HWPROBE_EXT_ZICCLSM (1ULL << 1) > > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 5cf463570229d..4b4a8157277a3 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -502,6 +502,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, > riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate), > __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, > riscv_ext_zicbop_validate), > __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, > riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate), > + __RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM), > __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE), > __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, > riscv_xlinuxenvcfg_exts, > riscv_cfilp_validate), > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > index f8f68ba781b45..9cf62266f1890 100644 > --- a/arch/riscv/kernel/sys_hwprobe.c > +++ b/arch/riscv/kernel/sys_hwprobe.c > @@ -205,6 +205,7 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair, > * in the hart_isa bitmap, are made. > */ > EXT_KEY(isainfo->isa, ZICFISS, pair->value, missing); > + EXT_KEY(isainfo->isa, ZICCLSM, pair->value, missing); > } > > /* Now turn off reporting features if any CPU is missing it. */ > > -- > 2.43.0 >
