There is a lot of code that is manually manipulating riscv instructions. Constructing these headers for new instructions is time consuming and error prone.
The first patch in this series introduces the instruction definition table along with a script that runs at compile time to create all of the associated instruction manipulation functions. The remaining patches migrate all of the manual instruction code to use these generated functions. The instruction definition table is generated from the riscv-unified-db[1], an open source RVI project for instruction specifications. I am sending this series at the same time as I am sending the patch to the riscv-unified-db for the format of the instruction table. That patch can be accessed on github [2]. A lot of the validation for these changes is from running all possible 32-bit or 16-bit integers through these functions to see that any given instruction will produce to expected result. I give more detail on the test cases in the notes of the first couple of patches. For the KVM patches, I also introduce two test cases to ensure that the instruction manipulation is working as expected, along with a bug fix of the current implemention. [1] https://github.com/riscv/riscv-unified-db [2] https://github.com/riscv/riscv-unified-db/pull/1780 Signed-off-by: Charlie Jenkins <[email protected]> --- Charlie Jenkins (16): riscv: Introduce instruction table generation riscv: alternatives: Use generated instruction headers for patching code riscv: kgdb: Use generated instruction headers riscv: kprobes: Use generated instruction headers riscv: cfi: Use generated instruction headers riscv: Use generated instruction headers for misaligned loads/stores riscv: kvm: Use generated instruction headers for csr code riscv: kvm: Fix MMIO emulation for sign-extended insns KVM: device: Add test device KVM: riscv: selftests: Add mmio test riscv: kvm: Use generated instruction headers for mmio emulation riscv: kvm: Add emulated test csr KVM: riscv: selftests: Add csr emulation test riscv: kvm: Use generated instruction headers for csr emulation riscv: kexec: Use generated instruction headers for kexec relocations riscv: Remove unused instruction headers arch/riscv/Kconfig.debug | 1 + arch/riscv/Makefile | 3 + arch/riscv/include/asm/Kbuild | 1 + arch/riscv/include/asm/insn.h | 563 +--------- arch/riscv/include/asm/kvm_host.h | 10 + arch/riscv/include/asm/kvm_vcpu_insn.h | 5 +- arch/riscv/include/asm/kvm_vcpu_test_csr.h | 15 + arch/riscv/kernel/alternative.c | 23 +- arch/riscv/kernel/cfi.c | 6 +- arch/riscv/kernel/kgdb.c | 102 +- arch/riscv/kernel/machine_kexec_file.c | 55 +- arch/riscv/kernel/probes/decode-insn.c | 7 +- arch/riscv/kernel/probes/simulate-insn.c | 253 ++--- arch/riscv/kernel/probes/simulate-insn.h | 7 +- arch/riscv/kernel/traps_misaligned.c | 183 ++-- arch/riscv/kvm/Kconfig.debug | 16 + arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu_insn.c | 233 ++--- arch/riscv/kvm/vcpu_test_csr.c | 21 + arch/riscv/tools/Makefile | 22 + arch/riscv/tools/insn.tbl | 1391 +++++++++++++++++++++++++ arch/riscv/tools/insn_tbl.sh | 263 +++++ include/uapi/linux/kvm.h | 2 + lib/Kconfig.debug | 6 + tools/testing/selftests/kvm/Makefile.kvm | 2 + tools/testing/selftests/kvm/riscv/csr_test.c | 123 +++ tools/testing/selftests/kvm/riscv/mmio_test.c | 184 ++++ virt/kvm/Kconfig.debug | 16 + virt/kvm/Makefile.kvm | 1 + virt/kvm/kvm_main.c | 8 + virt/kvm/mmio_test.c | 95 ++ virt/kvm/mmio_test.h | 18 + 32 files changed, 2624 insertions(+), 1012 deletions(-) --- base-commit: dd9b004b7ff3289fb7bae35130c0a5c0537266af change-id: ${change-id} - Charlie
