On Wed, Mar 18, 2026 at 06:17:00PM +0100, Cédric Bellegarde wrote: > dpu_encoder_toggle_vblank_for_crtc() can call control_vblank_irq() > at any time in response to a userspace vblank request, independently > of the atomic commit sequence. If this happens before the encoder's > first atomic_mode_set(), irq[INTR_IDX_RDPTR] is still zero. > > Passing irq_idx=0 to dpu_core_irq_register_callback() is treated as > invalid, and DPU_IRQ_REG(0) and DPU_IRQ_BIT(0) produce misleading > values of 134217727 and 31 respectively due to unsigned wraparound > in the (irq_idx - 1) macros, resulting in the confusing error: > > [dpu error]invalid IRQ=[134217727, 31] > > Since irq[INTR_IDX_RDPTR] will be properly populated by > atomic_mode_set() and registered by irq_enable() as part of the > normal modeset sequence, silently skip the vblank IRQ registration > when the index has not yet been initialized. This matches the > existing pattern of the master encoder check above it. > > Signed-off-by: Cédric Bellegarde <[email protected]> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 6 ++++++ > 1 file changed, 6 insertions(+) >
Reviewed-by: Dmitry Baryshkov <[email protected]> In future, please, don't post new iterations as replies to the previous one. See Documentation/process/submitting-patches.rst -- With best wishes Dmitry
