On Sat, Nov 8, 2025 at 1:42 PM Sergey Matyukevich <[email protected]> wrote: > > Add a test case to check ptrace behavior in the case when vector > extension is supported by the system, but vector context is not > yet enabled for the traced process. > > Signed-off-by: Sergey Matyukevich <[email protected]>
Reviewed-by: Andy Chiu <[email protected]> > --- > .../testing/selftests/riscv/vector/.gitignore | 1 + > tools/testing/selftests/riscv/vector/Makefile | 5 +- > .../testing/selftests/riscv/vector/v_ptrace.c | 85 +++++++++++++++++++ > 3 files changed, 90 insertions(+), 1 deletion(-) > create mode 100644 tools/testing/selftests/riscv/vector/v_ptrace.c > > diff --git a/tools/testing/selftests/riscv/vector/.gitignore > b/tools/testing/selftests/riscv/vector/.gitignore > index 7d9c87cd0649..d21c03c3ee0e 100644 > --- a/tools/testing/selftests/riscv/vector/.gitignore > +++ b/tools/testing/selftests/riscv/vector/.gitignore > @@ -2,3 +2,4 @@ vstate_exec_nolibc > vstate_prctl > v_initval > v_exec_initval_nolibc > +v_ptrace > diff --git a/tools/testing/selftests/riscv/vector/Makefile > b/tools/testing/selftests/riscv/vector/Makefile > index 6f7497f4e7b3..c14ad127e7fb 100644 > --- a/tools/testing/selftests/riscv/vector/Makefile > +++ b/tools/testing/selftests/riscv/vector/Makefile > @@ -2,7 +2,7 @@ > # Copyright (C) 2021 ARM Limited > # Originally tools/testing/arm64/abi/Makefile > > -TEST_GEN_PROGS := v_initval vstate_prctl > +TEST_GEN_PROGS := v_initval vstate_prctl v_ptrace > TEST_GEN_PROGS_EXTENDED := vstate_exec_nolibc v_exec_initval_nolibc > > include ../../lib.mk > @@ -26,3 +26,6 @@ $(OUTPUT)/v_initval: v_initval.c $(OUTPUT)/sys_hwprobe.o > $(OUTPUT)/v_helpers.o > $(OUTPUT)/v_exec_initval_nolibc: v_exec_initval_nolibc.c > $(CC) -nostdlib -static -include ../../../../include/nolibc/nolibc.h \ > -Wall $(CFLAGS) $(LDFLAGS) $^ -o $@ -lgcc > + > +$(OUTPUT)/v_ptrace: v_ptrace.c $(OUTPUT)/sys_hwprobe.o $(OUTPUT)/v_helpers.o > + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ > diff --git a/tools/testing/selftests/riscv/vector/v_ptrace.c > b/tools/testing/selftests/riscv/vector/v_ptrace.c > new file mode 100644 > index 000000000000..6a4b5a2ab4a2 > --- /dev/null > +++ b/tools/testing/selftests/riscv/vector/v_ptrace.c > @@ -0,0 +1,85 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +#include <sys/ptrace.h> > +#include <sys/types.h> > +#include <sys/wait.h> > +#include <sys/wait.h> > +#include <sys/uio.h> > +#include <unistd.h> > +#include <errno.h> > + > +#include <linux/ptrace.h> > +#include <linux/elf.h> > + > +#include "../../kselftest_harness.h" > +#include "v_helpers.h" > + > +volatile unsigned long chld_lock; > + > +TEST(ptrace_v_not_enabled) > +{ > + pid_t pid; > + > + if (!is_vector_supported()) > + SKIP(return, "Vector not supported"); > + > + chld_lock = 1; > + pid = fork(); > + ASSERT_LE(0, pid) > + TH_LOG("fork: %m"); > + > + if (pid == 0) { > + while (chld_lock == 1) > + asm volatile("" : : "g"(chld_lock) : "memory"); > + > + asm volatile ("ebreak" : : : ); > + } else { > + struct __riscv_v_regset_state *regset_data; > + unsigned long vlenb; > + size_t regset_size; > + struct iovec iov; > + int status; > + int ret; > + > + asm volatile("csrr %[vlenb], vlenb" : [vlenb] "=r"(vlenb)); > + > + ASSERT_GT(vlenb, 0) > + TH_LOG("vlenb is not valid: %lu\n", vlenb); > + > + /* attach */ > + > + ASSERT_EQ(0, ptrace(PTRACE_ATTACH, pid, NULL, NULL)); > + ASSERT_EQ(pid, waitpid(pid, &status, 0)); > + ASSERT_TRUE(WIFSTOPPED(status)); > + > + /* unlock */ > + > + ASSERT_EQ(0, ptrace(PTRACE_POKEDATA, pid, &chld_lock, 0)); > + > + /* resume and wait for ebreak */ > + > + ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL)); > + ASSERT_EQ(pid, waitpid(pid, &status, 0)); > + ASSERT_TRUE(WIFSTOPPED(status)); > + > + /* try to read vector registers from the tracee */ > + > + regset_size = sizeof(*regset_data) + vlenb * 32; > + regset_data = calloc(1, regset_size); > + > + iov.iov_base = regset_data; > + iov.iov_len = regset_size; > + > + /* V extension is available, but not yet enabled for the > tracee */ > + > + errno = 0; > + ret = ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, &iov); > + ASSERT_EQ(ENODATA, errno); > + ASSERT_EQ(-1, ret); > + > + /* cleanup */ > + > + ASSERT_EQ(0, kill(pid, SIGKILL)); > + } > +} > + > +TEST_HARNESS_MAIN > -- > 2.51.0 >
