Add bus clocks corresponding to peripheral clocks currently supported by the BCM281xx clock driver.
Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Artur Weber <[email protected]> --- Changes in v4: - Adapt to CLOCK_COUNT -> CLK_COUNT rename Changes in v3: - Adapt to CLOCK_COUNT defines being moved Changes in v2: - Add this patch (BCM281xx bus clocks) --- drivers/clk/bcm/clk-bcm281xx.c | 127 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 124 insertions(+), 3 deletions(-) diff --git a/drivers/clk/bcm/clk-bcm281xx.c b/drivers/clk/bcm/clk-bcm281xx.c index 62c3bf465625..13fd8a5ea8fa 100644 --- a/drivers/clk/bcm/clk-bcm281xx.c +++ b/drivers/clk/bcm/clk-bcm281xx.c @@ -59,7 +59,17 @@ static struct peri_clk_data pmu_bsc_var_data = { .trig = TRIGGER(0x0a40, 2), }; -#define BCM281XX_AON_CCU_CLK_COUNT (BCM281XX_AON_CCU_PMU_BSC_VAR + 1) +static struct bus_clk_data hub_timer_apb_data = { + .gate = HW_SW_GATE(0x0414, 18, 3, 2), + .hyst = HYST(0x0414, 10, 11), +}; + +static struct bus_clk_data pmu_bsc_apb_data = { + .gate = HW_SW_GATE(0x0418, 18, 3, 2), + .hyst = HYST(0x0418, 10, 11), +}; + +#define BCM281XX_AON_CCU_CLK_COUNT (BCM281XX_AON_CCU_PMU_BSC_APB + 1) static struct ccu_data aon_ccu_data = { BCM281XX_CCU_COMMON(aon, AON), @@ -70,6 +80,10 @@ static struct ccu_data aon_ccu_data = { KONA_CLK(aon, pmu_bsc, peri), [BCM281XX_AON_CCU_PMU_BSC_VAR] = KONA_CLK(aon, pmu_bsc_var, peri), + [BCM281XX_AON_CCU_HUB_TIMER_APB] = + KONA_CLK(aon, hub_timer_apb, bus), + [BCM281XX_AON_CCU_PMU_BSC_APB] = + KONA_CLK(aon, pmu_bsc_apb, bus), [BCM281XX_AON_CCU_CLK_COUNT] = LAST_KONA_CLK, }, }; @@ -178,7 +192,36 @@ static struct peri_clk_data hsic2_12m_data = { .trig = TRIGGER(0x0afc, 5), }; -#define BCM281XX_MASTER_CCU_CLK_COUNT (BCM281XX_MASTER_CCU_HSIC2_12M + 1) +static struct bus_clk_data sdio1_ahb_data = { + .gate = HW_SW_GATE(0x0358, 16, 1, 0), +}; + +static struct bus_clk_data sdio2_ahb_data = { + .gate = HW_SW_GATE(0x035c, 16, 1, 0), +}; + +static struct bus_clk_data sdio3_ahb_data = { + .gate = HW_SW_GATE(0x0364, 16, 1, 0), +}; + +static struct bus_clk_data sdio4_ahb_data = { + .gate = HW_SW_GATE(0x0360, 16, 1, 0), +}; + +static struct bus_clk_data usb_ic_ahb_data = { + .gate = HW_SW_GATE(0x0354, 16, 1, 0), +}; + +/* also called usbh_ahb */ +static struct bus_clk_data hsic2_ahb_data = { + .gate = HW_SW_GATE(0x0370, 16, 1, 0), +}; + +static struct bus_clk_data usb_otg_ahb_data = { + .gate = HW_SW_GATE(0x0348, 16, 1, 0), +}; + +#define BCM281XX_MASTER_CCU_CLK_COUNT (BCM281XX_MASTER_CCU_USB_OTG_AHB + 1) static struct ccu_data master_ccu_data = { BCM281XX_CCU_COMMON(master, MASTER), @@ -197,6 +240,20 @@ static struct ccu_data master_ccu_data = { KONA_CLK(master, hsic2_48m, peri), [BCM281XX_MASTER_CCU_HSIC2_12M] = KONA_CLK(master, hsic2_12m, peri), + [BCM281XX_MASTER_CCU_SDIO1_AHB] = + KONA_CLK(master, sdio1_ahb, bus), + [BCM281XX_MASTER_CCU_SDIO2_AHB] = + KONA_CLK(master, sdio2_ahb, bus), + [BCM281XX_MASTER_CCU_SDIO3_AHB] = + KONA_CLK(master, sdio3_ahb, bus), + [BCM281XX_MASTER_CCU_SDIO4_AHB] = + KONA_CLK(master, sdio4_ahb, bus), + [BCM281XX_MASTER_CCU_USB_IC_AHB] = + KONA_CLK(master, usb_ic_ahb, bus), + [BCM281XX_MASTER_CCU_HSIC2_AHB] = + KONA_CLK(master, hsic2_ahb, bus), + [BCM281XX_MASTER_CCU_USB_OTG_AHB] = + KONA_CLK(master, usb_otg_ahb, bus), [BCM281XX_MASTER_CCU_CLK_COUNT] = LAST_KONA_CLK, }, }; @@ -309,7 +366,51 @@ static struct peri_clk_data pwm_data = { .trig = TRIGGER(0x0afc, 15), }; -#define BCM281XX_SLAVE_CCU_CLK_COUNT (BCM281XX_SLAVE_CCU_PWM + 1) +static struct bus_clk_data uartb_apb_data = { + .gate = HW_SW_GATE(0x0400, 16, 1, 0), +}; + +static struct bus_clk_data uartb2_apb_data = { + .gate = HW_SW_GATE(0x0404, 16, 1, 0), +}; + +static struct bus_clk_data uartb3_apb_data = { + .gate = HW_SW_GATE(0x0408, 16, 1, 0), +}; + +static struct bus_clk_data uartb4_apb_data = { + .gate = HW_SW_GATE(0x040c, 16, 1, 0), +}; + +static struct bus_clk_data ssp0_apb_data = { + .gate = HW_SW_GATE(0x0410, 16, 1, 0), +}; + +static struct bus_clk_data ssp2_apb_data = { + .gate = HW_SW_GATE(0x0418, 16, 1, 0), +}; + +static struct bus_clk_data bsc1_apb_data = { + .gate = HW_SW_GATE(0x0458, 16, 1, 0), + .hyst = HYST(0x0458, 8, 9), +}; + +static struct bus_clk_data bsc2_apb_data = { + .gate = HW_SW_GATE(0x045c, 16, 1, 0), + .hyst = HYST(0x045c, 8, 9), +}; + +static struct bus_clk_data bsc3_apb_data = { + .gate = HW_SW_GATE(0x0484, 16, 1, 0), + .hyst = HYST(0x0484, 8, 9), +}; + +static struct bus_clk_data pwm_apb_data = { + .gate = HW_SW_GATE(0x0468, 16, 1, 0), + .hyst = HYST(0x0468, 8, 9), +}; + +#define BCM281XX_SLAVE_CCU_CLK_COUNT (BCM281XX_SLAVE_CCU_PWM_APB + 1) static struct ccu_data slave_ccu_data = { BCM281XX_CCU_COMMON(slave, SLAVE), @@ -334,6 +435,26 @@ static struct ccu_data slave_ccu_data = { KONA_CLK(slave, bsc3, peri), [BCM281XX_SLAVE_CCU_PWM] = KONA_CLK(slave, pwm, peri), + [BCM281XX_SLAVE_CCU_UARTB_APB] = + KONA_CLK(slave, uartb_apb, bus), + [BCM281XX_SLAVE_CCU_UARTB2_APB] = + KONA_CLK(slave, uartb2_apb, bus), + [BCM281XX_SLAVE_CCU_UARTB3_APB] = + KONA_CLK(slave, uartb3_apb, bus), + [BCM281XX_SLAVE_CCU_UARTB4_APB] = + KONA_CLK(slave, uartb4_apb, bus), + [BCM281XX_SLAVE_CCU_SSP0_APB] = + KONA_CLK(slave, ssp0_apb, bus), + [BCM281XX_SLAVE_CCU_SSP2_APB] = + KONA_CLK(slave, ssp2_apb, bus), + [BCM281XX_SLAVE_CCU_BSC1_APB] = + KONA_CLK(slave, bsc1_apb, bus), + [BCM281XX_SLAVE_CCU_BSC2_APB] = + KONA_CLK(slave, bsc2_apb, bus), + [BCM281XX_SLAVE_CCU_BSC3_APB] = + KONA_CLK(slave, bsc3_apb, bus), + [BCM281XX_SLAVE_CCU_PWM_APB] = + KONA_CLK(slave, pwm_apb, bus), [BCM281XX_SLAVE_CCU_CLK_COUNT] = LAST_KONA_CLK, }, }; -- 2.51.1
