Document the physical client IDs specific to Glymur SoCs. Physical client IDs are used on newer Qualcomm platforms including Glymur, since the Inter Process Communication Controller (IPCC) HW block no longer has the virtual to physical mapping in place.
Signed-off-by: Sibi Sankar <[email protected]> --- https://patchwork.kernel.org/project/linux-arm-msm/patch/[email protected]/ ^^ patch seems to assume physical IDs are common across SoCs but it doesn't seem to hold true on Glymur. include/dt-bindings/mailbox/qcom-ipcc.h | 61 +++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h b/include/dt-bindings/mailbox/qcom-ipcc.h index fd85a79381b3..61cef29e43f0 100644 --- a/include/dt-bindings/mailbox/qcom-ipcc.h +++ b/include/dt-bindings/mailbox/qcom-ipcc.h @@ -36,4 +36,65 @@ #define IPCC_CLIENT_GPDSP0 31 #define IPCC_CLIENT_GPDSP1 32 +/* Platform specific physical client IDs */ + +/* Glymur physical client IDs */ +#define GLYMUR_MPROC_AOP 0 +#define GLYMUR_MPROC_TZ 1 +#define GLYMUR_MPROC_MPSS 2 +#define GLYMUR_MPROC_LPASS 3 +#define GLYMUR_MPROC_SLPI 4 +#define GLYMUR_MPROC_SDC 5 +#define GLYMUR_MPROC_CDSP 6 +#define GLYMUR_MPROC_NPU 7 +#define GLYMUR_MPROC_APSS 8 +#define GLYMUR_MPROC_GPU 9 +#define GLYMUR_MPROC_ICP 11 +#define GLYMUR_MPROC_VPU 12 +#define GLYMUR_MPROC_PCIE0 13 +#define GLYMUR_MPROC_PCIE1 14 +#define GLYMUR_MPROC_PCIE2 15 +#define GLYMUR_MPROC_SPSS 16 +#define GLYMUR_MPROC_PCIE3 19 +#define GLYMUR_MPROC_PCIE4 20 +#define GLYMUR_MPROC_PCIE5 21 +#define GLYMUR_MPROC_PCIE6 22 +#define GLYMUR_MPROC_TME 23 +#define GLYMUR_MPROC_WPSS 24 +#define GLYMUR_MPROC_PCIE7 44 +#define GLYMUR_MPROC_SOCCP 46 + +#define GLYMUR_COMPUTE_L0_LPASS 0 +#define GLYMUR_COMPUTE_L0_CDSP 1 +#define GLYMUR_COMPUTE_L0_APSS 2 +#define GLYMUR_COMPUTE_L0_GPU 3 +#define GLYMUR_COMPUTE_L0_CVP 6 +#define GLYMUR_COMPUTE_L0_ICP 7 +#define GLYMUR_COMPUTE_L0_VPU 8 +#define GLYMUR_COMPUTE_L0_DPU 9 +#define GLYMUR_COMPUTE_L0_SOCCP 11 + +#define GLYMUR_COMPUTE_L1_LPASS 0 +#define GLYMUR_COMPUTE_L1_CDSP 1 +#define GLYMUR_COMPUTE_L1_APSS 2 +#define GLYMUR_COMPUTE_L1_GPU 3 +#define GLYMUR_COMPUTE_L1_CVP 6 +#define GLYMUR_COMPUTE_L1_ICP 7 +#define GLYMUR_COMPUTE_L1_VPU 8 +#define GLYMUR_COMPUTE_L1_DPU 9 +#define GLYMUR_COMPUTE_L1_SOCCP 11 + +#define GLYMUR_PERIPH_LPASS 0 +#define GLYMUR_PERIPH_APSS 1 +#define GLYMUR_PERIPH_PCIE0 2 +#define GLYMUR_PERIPH_PCIE1 3 +#define GLYMUR_PERIPH_PCIE2 6 +#define GLYMUR_PERIPH_PCIE3 7 +#define GLYMUR_PERIPH_PCIE4 8 +#define GLYMUR_PERIPH_PCIE5 9 +#define GLYMUR_PERIPH_PCIE6 10 +#define GLYMUR_PERIPH_PCIE7 11 +#define GLYMUR_PERIPH_SOCCP 13 +#define GLYMUR_PERIPH_WPSS 16 + #endif -- 2.34.1
