On Thu, Apr 01, 2021 at 05:10:28PM -0700, [email protected] wrote: > From: Ricardo Neri <[email protected]> > > Add feature enumeration to identify a processor with Intel Hybrid > Technology: one in which CPUs of more than one type are the same package. > On a hybrid processor, all CPUs support the same homogeneous (i.e., > symmetric) instruction set. All CPUs enumerate the same features in CPUID. > Thus, software (user space and kernel) can run and migrate to any CPU in > the system as well as utilize any of the enumerated features without any > change or special provisions. The main difference among CPUs in a hybrid > processor are power and performance properties. > > Cc: Andi Kleen <[email protected]> > Cc: Kan Liang <[email protected]> > Cc: "Peter Zijlstra (Intel)" <[email protected]> > Cc: "Rafael J. Wysocki" <[email protected]> > Cc: "Ravi V. Shankar" <[email protected]> > Cc: Srinivas Pandruvada <[email protected]> > Cc: [email protected] > Reviewed-by: Len Brown <[email protected]> > Reviewed-by: Tony Luck <[email protected]> > Signed-off-by: Ricardo Neri <[email protected]> > --- > Changes since v3 (as part of patchset for perf change for Alderlake) > * None > > Changes since V2 (as part of patchset for perf change for Alderlake) > * Don't show "hybrid_cpu" in /proc/cpuinfo (Boris) > > Changes since v1 (as part of patchset for perf change for Alderlake) > * None > > Changes since v1 (in a separate posting): > * Reworded commit message to clearly state what is Intel Hybrid > Technology. Stress that all CPUs can run the same instruction > set and support the same features. > --- > arch/x86/include/asm/cpufeatures.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h > b/arch/x86/include/asm/cpufeatures.h > index cc96e26d69f7..1ba4a6e1690c 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -374,6 +374,7 @@ > #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */ > #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */ > #define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE > instruction */ > +#define X86_FEATURE_HYBRID_CPU (18*32+15) /* "" This part has > CPUs of more than one type */ > #define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address > Tracking */ > #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ > #define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */ > --
Acked-by: Borislav Petkov <[email protected]> -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette
