On Fri, Jan 15, 2021 at 05:22:07PM +0800, Zhang Rui wrote: > In the RAPL ENERGY_COUNTER MSR, only the lower 32bits represent the > energy counter, and the higher 32bits are reserved. > > Add the MSR mask for these MSRs to fix a problem that the RAPL PMU events > are added erroneously when higher 32bits contain non-zero value.
Why would these high bits be non-zero?
