On Wed, Dec 19, 2007 at 11:48:14AM -0800, H. Peter Anvin wrote: > Ingo Molnar wrote: > > > >i dont think it's required for C3 to even turn off any portion of the > >CPU - if an interrupt arrives after the C3 sequence is initiated but > >just before dirty cachelines have been flushed then the CPU can just > >return without touching anything (such as the TLB) - right? So i dont > >think there's any implicit guarantee of TLB flushing (nor should there > >be), but in practice, a good C3 sequence would (statistically) turn off > >large portions of the CPU and hence the TLB as well. > > > > I think C3 guarantees that the cache contents stay intact, and thus it > might make sense in some technology to preserve the TLB as well (being a > kind of cache.) > > Otherwise, what you say here of course is absolutely correct. >
C3 does not guarantee all cache contents. Infact, atleast on Intel, L1 will be almost always flushed. Newer more power efficient CPUs does dynamic cache sizing [1] C3 just guarantees that the caches are coherent. That is, if they are intact, then DMA will keep cache consistent. Thanks, Venki [1] - http://download.intel.com/products/processor/core2duo/mobile_prod_brief.pdf -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
