The following commit has been merged into the perf/core branch of tip: Commit-ID: b14d0db5b8c86507c9810c1c8162c7d4a3c656bd Gitweb: https://git.kernel.org/tip/b14d0db5b8c86507c9810c1c8162c7d4a3c656bd Author: Kan Liang <[email protected]> AuthorDate: Mon, 19 Oct 2020 08:35:25 -07:00 Committer: Peter Zijlstra <[email protected]> CommitterDate: Thu, 29 Oct 2020 11:00:39 +01:00
perf/x86/intel: Add Rocket Lake CPU support >From the perspective of Intel PMU, Rocket Lake is the same as Ice Lake and Tiger Lake. Share the perf code with them. Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Link: https://lkml.kernel.org/r/[email protected] --- arch/x86/events/intel/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 7186098..4d70c7d 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5436,6 +5436,7 @@ __init int intel_pmu_init(void) case INTEL_FAM6_ICELAKE: case INTEL_FAM6_TIGERLAKE_L: case INTEL_FAM6_TIGERLAKE: + case INTEL_FAM6_ROCKETLAKE: x86_pmu.late_ack = true; memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
