Quoting Serge Semin (2020-09-20 04:03:35) > We've discovered that disabling the so called Ethernet PLL causes reset of > the devices consuming its outgoing clock. The resets happen automatically > even if each underlying clock gate is turned off. Due to that we can't > disable the Ethernet PLL until the kernel is prepared for the corresponding > resets. So for now just mark the PLL clock provider as critical. > > Signed-off-by: Serge Semin <[email protected]> > Cc: Alexey Malahov <[email protected]> > Cc: [email protected] > ---
Applied to clk-next
