Am Donnerstag 15 November 2007 schrieb Maciej W. Rozycki:
> On Thu, 15 Nov 2007, Oliver Neukum wrote:
>
> > is there a way to so misprogramm an APIC that a physical interrupt results
> > in two interrupts delivered?
>
> Certainly. One possibility is to have multiple processors marked as the
> destination, e.g. a logical delivery mode destination programmed with
> multiple bits set.
What would be the consequences?
I am seeing an interrupt for an UHCI on #20 CPU1 also arriving on
#19 CPU0, triggering the spurious interrupt detection.
Regards
Oliver
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