From: Zhanyong Wang <[email protected]>

Add SSUSB related nodes for mt8192

Signed-off-by: Zhanyong Wang <[email protected]>
Signed-off-by: Chunfeng Yun <[email protected]>
---
Depends on:
https://patchwork.kernel.org/patch/11713559/
[v4,1/3] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and 
Makefile
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 48 ++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 8871c2f..755f152 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -434,6 +434,54 @@
                        status = "disabled";
                };
 
+               xhci: xhci@11200000 {
+                       compatible = "mediatek,mt8192-xhci",
+                                    "mediatek,mtk-xhci";
+                       reg = <0 0x11200000 0 0x1000>,
+                             <0 0x11203e00 0 0x0100>;
+                       reg-names = "mac", "ippc";
+                       interrupts-extended = <&gic GIC_SPI 97 
IRQ_TYPE_LEVEL_HIGH 0>,
+                                             <&pio 211 IRQ_TYPE_LEVEL_LOW>;
+                       phys = <&u2port0 PHY_TYPE_USB2>,
+                              <&u3port0 PHY_TYPE_USB3>;
+                       assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
+                                         <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
+                       assigned-clock-parents = <&topckgen 
CLK_TOP_UNIVPLL_D5_D4>,
+                                                <&topckgen 
CLK_TOP_UNIVPLL_D5_D4>;
+                       clocks = <&infracfg CLK_INFRA_SSUSB>,
+                                <&infracfg CLK_INFRA_SSUSB_XHCI>,
+                                <&apmixedsys CLK_APMIXED_USBPLL>;
+                       clock-names = "sys_ck", "xhci_ck", "ref_ck";
+                       mediatek,syscon-wakeup = <&pericfg 0x420 3>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+               };
+
+               u3phy0: usb-phy@11e40000 {
+                       compatible = "mediatek,mt8192-tphy",
+                                    "mediatek,generic-tphy-v2";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       status = "okay";
+
+                       u2port0: usb-phy@11e40000 {
+                               reg = <0 0x11e40000 0 0x700>;
+                               clocks = <&clk26m>;
+                               clock-names = "ref";
+                               #phy-cells = <1>;
+                               status = "okay";
+                       };
+
+                       u3port0: usb-phy@11e40700 {
+                               reg = <0 0x11e40700 0 0x900>;
+                               clocks = <&clk26m>;
+                               clock-names = "ref";
+                               #phy-cells = <1>;
+                               status = "okay";
+                       };
+               };
+
                audsys: syscon@11210000 {
                        compatible = "mediatek,mt8192-audsys", "syscon";
                        reg = <0 0x11210000 0 0x1000>;
-- 
1.9.1

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